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26HS01GTAM03 Datasheet(PDF) 111 Page - Infineon Technologies AG |
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26HS01GTAM03 Datasheet(HTML) 111 Page - Infineon Technologies AG |
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111 / 166 page ![]() Datasheet 111 of 166 002-12337 Rev. *Y 2022-01-18 256Mb/512Mb/1Gb SEMPER™ Flash HYPERBUS™ interface, 1.8V/3.0V Registers Table 97 Latency code (Cycles) versus frequency[27, 28, 30] Latency code CR Number of cycles SDR SPI read transactions (MHz) (1S-1S-1S) RDAY2_C_0 RDSSR_4_0 RDARG_4_0[29] RDECC_4_0 RDPPB_4_0 0000 0 50 0001 1 68 0010 2 81 0011 3 93 0100 4 106 0101 5 118 0110 6 131 0111 7 143 1000 8 156 1001 9 166 1010 10 166 1011 11 166 1100 12 166 1101 13 166 1110 14 166 1111 15 166 Notes 27. When using the ECC error reporting mechanisms, the read output data must be at least 2 bytes for correct ECC reporting. 28. SCK frequency > 200MHz SDR, or > 200MHz DDR is not supported by HS-T family of devices and SCK frequency > 166MHz SDR, or > 166MHz DDR is not supported by HL-T family of devices. 29. RDARG_4_0 uses these latency cycles for reading Nonvolatile registers. 30. RSFDP_3_0 always have a dummy cycle of eight and the maximum frequencies for different interfaces related to eight dummy cycles. |
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