26HS01GTAM03 datasheet(117/166 Pages) INFINEON

117 / 166 page

Datasheet

117 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Registers

5.3.11

ECC address trap register (EATV) (x1)

The ECC Address Trap Register (EATV) stores the address of the ECC unit data where either a 1-Bit/2-Bit error or

only a 1-Bit error occurred during a read operation. It stores the ECC unit address of the first ECC error captured

during a memory read operation since the last Clear ECC transaction.

5.3.12

ECC error detection count register (ECTV) (x1)

The ECC Error Detection Counter Register (ECTV) stores the number of either 1-Bit/2-Bit or only 1-Bit ECC errors

have occurred during read operations since the last POR or hardware/software reset.

5.3.13

Advanced sector protection register (ASPO) (x1)

The ASP Register (ASPO) configures the behavior of Advanced Sector Protection scheme.

Table 106

ECC address trap register (x1)

Bit number

Name

Function

Read/write

N = Nonvolatile

V = Volatile

Factory

default

(hex)

Description

EATV[31:0]

ECCATP[31:0]

ECC 1-bit and 2-bit Error

Address Trap Register

V -> R

0x00000000

Description: The Address Trap Register (ECCATP[31:0])

stores the ECC unit data address where a 1-Bit/2-Bit

error occurred during a read operation. ECCATP[31:0]

stores the ECC unit address of the first ECC error

captured during a memory read operation since the

last Clear ECC Status Register transaction

(CLECC_0_0).

Note ECCATP[31:0] is only updated during Read

Instruction.

Note Clear ECC Status Register transaction

(CLECC_0_0), POR or Hardware/Software reset clears

the EATV[31:0] to 0x00000000.

Selection Options: ECC Error Data Unit Address

Dependency: N/A

Table 107

ECC count register (x1)

Bit number

Name

Function

Read/write

N = Nonvolatile

V = Volatile

Factory

default

(hex)

Description

ECTV[15:0]

ECCCNT[15:0]

ECC 1-bit and 2-bit Error

Count Register

V -> R

0x0000

Description: The ECCCNT[15:0] stores the number of

1-bit/2-bit ECC errors occurred during read operations

since the last POR or hardware/software reset.

Note ECCCNT[15:0] is only updated during Read

Instruction.

Note Only one ECC error is counted for each data unit.

If multiple read transactions access the same unit data

containing an ECC error, the ECCCNT[15:0] will

increment each time the unit data is read.

Note Once the count reaches 0xFFFF, the ECCCNT[15:0]

will stop incrementing

Note POR or Hardware/Software reset clears the

ECCNT[15:0] to 0x0000.

Selection Options: ECC Error Count

Dependency: N/A

Table 108

Advanced sector protection register (x1)

Bit number

Name

Function

Read/write

N = Nonvolatile

V = Volatile

Factory

default

(binary)

Description

ASPO[15:6]

RESRVD

Reserved for Future Use

N => R/1

1111111111 This bit is Reserved for future use. This bit must always be

written/loaded to its default state.

ASPO[5]

ASPRDP

Read Password Based

Protection Selection

N => R/1

Description: The ASPRDP bit selects the Read Password

Mode Protection mode. Read Password Protection mode

works in conjunction with Password Protection mode to

protect all sectors from Read/Erase/Program. Based on

TBPROT configuration bit (CFR1x[5]), either the top or

bottom sector is available for reading.

Selection Options:

0 = Read Password Protection Mode is enabled

1 = Read Password Protection Mode is disabled

Dependency: TBPROT (CFR1x[5])

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