26HS01GTAM03 datasheet(106/166 Pages) INFINEON

106 / 166 page

Datasheet

106 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Registers

5.3

Legacy (x1) SPI registers

5.3.1

Status register 1 (STR1x) (x1)

Status Register 1 contains both status and control bits. The functionality of supported Status Register 1 type is

described in Table 91.

Table 91

Status register 1 (x8)[25]

Bit number

Name

Function

Read/write

N = Nonvolatile

V = Volatile

Factory

default

(binary)

Description

STR1N[7]

STR1V[7]

RESRVD

Reserved for Future Use

N->R

V->R

This bit is Reserved for future use. This bit must always be

written/loaded to its default state.

STR1V[6]

PRGERR

Programming Error

Status Flag

V -> R

Description: The PRGERR bit indicates program operation

success or failure. When the PRGERR bit is set to a ‘1’, it

indicates that there was an error in the last programming

operation. PRGERR bit is also set when a program operation

is attempted within a protected memory region. When

PRGERR is set, it can only be cleared with the Clear Status

reset.

Note The device will only go to standby mode once the

PRGERR flag is cleared.

Selection Options:

0 = Last programming operation was successful

1 = Last programming operation was unsuccessful

Dependency: N/A

STR1V[5]

ERSERR

Erasing Error Status

Flag

V -> R

Description: The ERSERR bit indicates erase operation

success or failure. When the ERSERR bit is set to a ‘1’, it

indicates that there was an error in the last erasing

operation. ERSERR bit is also set when a erase operation is

attempted within a protected memory sector. When

ERSERR is set, it can only be cleared with the Clear Status

reset.

Note The device will only go to standby mode once the

ERSERR flag is cleared.

Selection Options:

0 = Last erase operation was successful

1 = Last erase operation was unsuccessful

Dependency: N/A

STR1N[4:2]

STR1V[4:2]

RESRVD

Reserved for Future Use

N->R

V -> R

000

These bits are Reserved for future use. They must always be

written/loaded to their default state.

Note

25. STR1x value during POR, Hardware Reset, DPD Exit, and CS# Signaling Reset is not valid.

26HS01GTAM03 Datasheet(PDF) 106 Page - Infineon Technologies AG

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