26HS01GTAM03 datasheet(105/166 Pages) INFINEON

105 / 166 page

Datasheet

105 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Registers

5.2.19

INT# pin status register (INSV) (x8)

The INT# Pin Status Register (INSV) indicates which internal event(s) has occurred since the last time the ISR was

cleared.

INCV[1]

ECC2BT

ECC 2-bit Error

Detection Selection

V => R/W

Description: The ECC2BT bit enables or disables

whether a 2-bit ECC detection error will transition INT#.

Selection Options:

0 = 2-bit ECC detection will cause a High to Low

transition the INT# output

1 = 2-bit ECC detection will not transition the INT#

output

Dependency: N/A

INCV[0]

ECC1BT

ECC 1-bit Error

Detection and

Correction Selection

V => R/W

Description: The ECC1BT bit enables or disables

whether a 1-bit ECC detection and correction error will

transition INT#.

Selection Options:

0 = 1-bit ECC detection and correction will cause a High

to Low transition the INT# output

1 = 1-bit ECC detection and correction will not transition

the INT# output

Dependency: N/A

Table 90

Interrupt status register (x8)

Bit number

Name

Function

Read/write

N = Nonvolatile

V = Volatile

Factory

default

(binary)

Description

INSV[15:5]

RESRVD

Reserved for Future Use

V => R/W

1111111111

These bits are Reserved for future use. This bit must

always be written/loaded to its default state.

INSV[4]

REYBSY

Ready/Busy Transition

V => R/W

Description: The REYBSY bit indicates whether the

device's ready/busy status has caused a transition on

INT#.

Selection Options:

0 = A Busy to Ready transition has occurred

1 = A Busy to Ready transition has not occurred

Dependency: N/A

INSV[3:2]

RESRVD

Reserved for Future Use

V => R/W

These bits are Reserved for future use. This bit must

always be written/loaded to its default state.

INSV[1]

ECC2BT

ECC 2-bit Error

Detection

V => R/W

Description: The ECC2BT bit indicates whether a 2-bit

ECC detection error has caused a transition on INT#.

Selection Options:

0 = 2-bit error detection has occurred

1 = 2-bit error detection has not occurred

Dependency: N/A

INSV[0]

ECC1BT

ECC 1-bit Error

Detection and

Correction

V => R/W

Description: The ECC1BT bit indicates whether a 1-bit

ECC correction error has caused a transition on INT#.

Selection Options:

0 = 1-bit error correction has occurred

1 = 1-bit error correction has not occurred

Dependency: N/A

Table 89

Interrupt configuration register (x8) (Continued)

Bit number

Name

Function

Read/write

N = Nonvolatile

V = Volatile

Factory

default

(binary)

Description

26HS01GTAM03 Datasheet(PDF) 105 Page - Infineon Technologies AG

26HS01GTAM03 Datasheet(HTML) 105 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL