R5F72115D160FPV datasheet(439/1228 Pages) RENESAS

439 / 1228 page

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 May. 08, 2008 Page 415 of 1200

REJ09B0344-0200

10.3.17

Timer Counter Synchronous Start Register (TCSYSTR)

TCSYSTR is an 8-bit readable/writable register that specifies synchronous start of the MTU2 and

MTU2S counters. Note that the MTU2S does not have TCSYSTR.

Bit:

Initial value:

R/W:

7654321

00000000

R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*

R/(W)* R/(W)*

Note:

Only 1 can be written to set the register.

SCH0

SCH1

SCH2

SCH3

SCH4

SCH3S SCH4S

Bit

Bit Name

Initial

Value

R/W

Description

SCH0

R/(W)* Synchronous Start

Controls synchronous start of TCNT_0 in the MTU2.

0: Does not specify synchronous start for TCNT_0 in

the MTU2

1: Specifies synchronous start for TCNT_0 in the MTU2

[Clearing condition]

• When 1 is set to the CST0 bit of TSTR in MTU2

while SCH0 = 1

SCH1

R/(W)* Synchronous Start

Controls synchronous start of TCNT_1 in the MTU2.

0: Does not specify synchronous start for TCNT_1 in

the MTU2

1: Specifies synchronous start for TCNT_1 in the MTU2

[Clearing condition]

• When 1 is set to the CST1 bit of TSTR in MTU2

while SCH1 = 1

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