EP4CE40 datasheet(214/488 Pages) ALTERA

214 / 488 page

8–50

Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices

Configuration

Cyclone IV Device Handbook,

May 2013

Altera Corporation

Volume 1

When programming a JTAG device chain, one JTAG-compatible header is connected

to several devices. The number of devices in the JTAG chain is limited only by the

drive capability of the download cable. When four or more devices are connected in a

JTAG chain, Altera recommends buffering the TCK, TDI, and TMS pins with an on-board

buffer.

JTAG-chain device programming is ideal when the system contains multiple devices,

or when testing your system with JTAG BST circuitry. Figure 8–25 and Figure 8–26

show multi-device JTAG configuration.

For devices using 2.5-, 3.0-, and 3.3-V VCCIO supply, you must refer to Figure 8–25. All

I/O inputs must maintain a maximum AC voltage of 4.1 V because JTAG pins do not

have the internal PCI clamping diodes to prevent voltage overshoot when using 2.5-,

3.0-, and 3.3- V VCCIO supply. You must power up the VCC of the download cable with

a 2.5-V VCCA supply. For device using VCCIO of 1.2, 1.5 V, and 1.8 V, refer to

Figure 8–26. You can power up the VCC of the download cable with the supply from

VCCIO.

Figure 8–25. JTAG Configuration of Multiple Devices Using a Download Cable (2.5, 3.0, and 3.3-V VCCIO Powering the

JTAG Pins)

Notes to Figure 8–25:

(1) Connect these pull-up resistors to the VCCIO supply of the bank in which the pin resides.

(2) Connect the nCONFIG and MSEL pins to support a non-JTAG configuration scheme. If you only use a JTAG configuration, connect the nCONFIG

pin to logic-high and the MSEL pins to GND. In addition, pull DCLK and DATA[0] to either high or low, whichever is convenient on your board.

(3) Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO must match the VCCA of the device. For this value, refer to the

MasterBlaster Serial/USB Communications Cable User Guide. In the ByteBlasterMV cable, this pin is a no connect. In the USB-Blaster and

ByteBlaster II cables, this pin is connected to nCE when it is used for AS programming, otherwise it is a no connect.

(4) You must connect the nCE pin to GND or driven low for successful JTAG configuration.

(5) Power up the VCC of the ByteBlaster II, USB-Blaster, or ByteBlasterMV cable with a 2.5-V supply from VCCA. Third-party programmers must switch

to 2.5 V. Pin 4 of the header is a VCC power supply for the MasterBlaster cable. The MasterBlaster cable can receive power from either 5.0- or 3.3-V

circuit boards, DC power supply, or 5.0 V from the USB cable. For this value, refer to the MasterBlaster Serial/USB Communications Cable User

Guide.

(6) Resistor value can vary from 1 k

Ω to 10 kΩ.

TMS

TCK

Download Cable

10-Pin Male Header

TDI

TDO

Pin 1

nST

ATUS

nCONFIG

nCE (4)

CONF_DONE

VCCIO

(2)

VIO

(3)

(6)

(1)

(2)

DATA[0]

DCLK

(2)

MSEL[ ]

nCEO

(2)

TMS

TCK

TDI

TDO

nST

ATUS

nCONFIG

nCE (4)

CONF_DONE

(2)

(1)

(2)

DATA[0]

DCLK

(2)

nCEO

(2)

(1)

TMS

TCK

TDI

TDO

nST

ATUS

nCONFIG

nCE (4)

VCCIO

VCCA

CONF_DONE

(2)

DATA[0]

DCLK

(2)

nCEO

(2)

(1)

10 k

Cyclone IV Device

VCCIO

(5)

MSEL[ ]

VCCA

1 k

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