TMS320F2810PBKA datasheet(116/173 Pages) TI

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116

TMS320F2810, TMS320F2811, TMS320F2812

SPRS174U – APRIL 2001 – REVISED JULY 2019

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Detailed Description

Table 6-9. McBSP Registers (continued)

NAME

ADDRESS

0x00 78xxh

TYPE

(R/W)

RESET VALUE

(HEX)

DESCRIPTION

(2)

FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.

FIFO MODE REGISTERS (applicable only in FIFO mode)

FIFO Data Registers(2)

DRR2

0x0000

McBSP Data Receive Register 2 – Top of receive FIFO

•

Read First FIFO pointers will not advance

DRR1

0x0000

McBSP Data Receive Register 1 – Top of receive FIFO

•

Read Second for FIFO pointers to advance

DXR2

0x0000

McBSP Data Transmit Register 2 – Top of transmit FIFO

•

Write First FIFO pointers will not advance

DXR1

0x0000

McBSP Data Transmit Register 1 – Top of transmit FIFO

•

Write Second for FIFO pointers to advance

FIFO Control Registers

MFFTX

R/W

0xA000

McBSP Transmit FIFO Register

MFFRX

R/W

0x201F

McBSP Receive FIFO Register

MFFCT

R/W

0x0000

McBSP FIFO Control Register

MFFINT

R/W

0x0000

McBSP FIFO Interrupt Register

MFFST

R/W

0x0000

McBSP FIFO Status Register

TMS320F2810PBKA Datasheet(PDF) 116 Page - Texas Instruments

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