TMS320F2810PBKA datasheet(117/173 Pages) TI

117 / 173 page

rate

Baud

(BRR

LSPCLK

BRR

when

LSPCLK

BRR

when

117

TMS320F2810, TMS320F2811, TMS320F2812

www.ti.com

SPRS174U – APRIL 2001 – REVISED JULY 2019

Submit Documentation Feedback

Product Folder Links: TMS320F2810 TMS320F2811 TMS320F2812

Detailed Description

(1)

Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is

less than the I/O buffer speed limit—20 MHz maximum.

6.2.6

Serial Communications Interface (SCI) Module

The F281x devices include two serial communications interface (SCI) modules. The SCI modules support

digital communications between the CPU and other asynchronous peripherals that use the standard non-

return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own

separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-

duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun,

and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud-

select register.

Features of each SCI module include:

•

Two external pins:

–

SCITXD: SCI transmit-output pin

–

SCIRXD: SCI receive-input pin

NOTE: Both pins can be used as GPIO if not used for SCI.

•

Baud rate programmable to 64K different rates (1)

•

Data-word format

–

One start bit

–

Data-word length programmable from one to eight bits

–

Optional even/odd/no parity bit

–

One or two stop bits

•

Four error-detection flags: parity, overrun, framing, and break detection

•

Two wake-up multiprocessor modes: idle-line and address bit

•

Half- or full-duplex operation

•

Double-buffered receive and transmit functions

•

Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms

with status flags.

–

Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX

EMPTY flag (transmitter-shift register is empty)

–

Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag

(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)

•

Separate enable bits for transmitter and receiver interrupts (except BRKDT)

•

Max bit rate = 75 MHz/16 = 4.688 x 106 b/s

•

NRZ (non-return-to-zero) format

•

Ten SCI module control registers located in the control register frame beginning at address 7050h

NOTE: All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When

a register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as

zeros. Writing to the upper byte has no effect.

Enhanced features:

•

Auto baud-detect hardware logic

•

16-level transmit/receive FIFO

TMS320F2810PBKA Datasheet(PDF) 117 Page - Texas Instruments

TMS320F2810PBKA Datasheet(HTML) 117 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL