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TMS320F2810PBKA Datasheet(PDF) 125 Page - Texas Instruments

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Part # TMS320F2810PBKA
Description  TMS320F281x Digital Signal Processors
PDF  173 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320F2810PBKA Datasheet(HTML) 125 Page - Texas Instruments

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Peripheral I/O
MUX
0
1
MUX
1
0
PIN
Internal (Pullup or Pulldown)
Digital I/O
XRS
High-Impedance
Enable (1)
High-
Impedance
Control
GPxDIR
Register Bit
GPxMUX
Register Bit
GPxQUAL
Register
GPxDAT/SET/CLEAR/TOGGLE
Register Bit(s)
Input Qualification
SYSCLKOUT
125
TMS320F2810, TMS320F2811, TMS320F2812
www.ti.com
SPRS174U – APRIL 2001 – REVISED JULY 2019
Submit Documentation Feedback
Product Folder Links: TMS320F2810 TMS320F2811 TMS320F2812
Detailed Description
Copyright © 2001–2019, Texas Instruments Incorporated
Figure 6-12 shows how the various register bits select the various modes of operation for GPIO function.
A.
In the GPIO mode, when the GPIO pin is configured for output operation, reading the GPxDAT data register only
gives the value written, not the value at the pin. In the peripheral mode, the state of the pin can be read through the
GPxDAT register, provided the corresponding direction bit is zero (input mode).
B.
Some selected input signals are qualified by the SYSCLKOUT. The GPxQUAL register specifies the qualification
sampling period. The sampling window is 6 samples wide and the output is only changed when all samples are the
same (all 0's or all 1's). This feature removes unwanted spikes from the input signal.
Figure 6-12. GPIO/Peripheral Pin Multiplexing
NOTE
The input function of the GPIO pin and the input path to the peripheral are always enabled. It
is the output function of the GPIO pin that is multiplexed with the output path of the primary
(peripheral) function. Since the output buffer of a pin connects back to the input buffer, any
GPIO signal present at the pin will be propagated to the peripheral module as well.
Therefore, when a pin is configured for GPIO operation, the corresponding peripheral
functionality (and interrupt-generating capability) must be disabled. Otherwise, interrupts may
be inadvertently triggered. This is especially critical when the PDPINTA and PDPINTB pins
are used as GPIO pins, since a value of zero for GPDDAT.0 or GPDDAT.5 (PDPINTx) will
put PWM pins in a high-impedance state. The CxTRIP and TxCTRIP pins will also put the
corresponding PWM pins in high impedance, if they are driven low (as GPIO pins) and bit
EXTCONx.0 = 1.



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