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TMS320F2810PBKA Datasheet(PDF) 134 Page - Texas Instruments

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Part # TMS320F2810PBKA
Description  TMS320F281x Digital Signal Processors
PDF  173 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320F2810PBKA Datasheet(HTML) 134 Page - Texas Instruments

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XD[15:0]
XA[18:0]
XZCS6
XZCS7
XZCS6AND7
XZCS2
XWE
XR/W
XREADY
XMP/MC
XHOLD
XHOLDA
XCLKOUT
(E)
XRD
XINTF Zone 0
(8K x 16)
XINTF Zone 1
(8K x 16)
XINTF Zone 2
(512K x 16)
XINTF Zone 6
(512K x 16)
XINTF Zone 7
(16K x 16)
(mapped here if MP/
= 1)
MC
0x40 0000
0x3F C000
0x18 0000
0x10 0000
0x00 6000
0x00 4000
0x00 2000
0x00 0000
Data Space
Prog Space
0x08 0000
XZCS0AND1
XZCS0
XZCS1
134
TMS320F2810, TMS320F2811, TMS320F2812
SPRS174U – APRIL 2001 – REVISED JULY 2019
www.ti.com
Submit Documentation Feedback
Product Folder Links: TMS320F2810 TMS320F2811 TMS320F2812
Detailed Description
Copyright © 2001–2019, Texas Instruments Incorporated
6.6
External Interface, XINTF (F2812 Only)
This section gives a top-level view of the external interface (XINTF) that is implemented on the F2812
device.
The external interface is a non-multiplexed asynchronous bus, similar to the C240x external interface. The
external interface on the F2812 is mapped into five fixed zones shown in Figure 6-16.
Figure 6-16 shows the F2812 XINTF signals.
A.
The mapping of XINTF Zone 7 is dependent on the XMP/MC device input signal and the MP/MC mode bit (bit 8 of
XINTCNF2 register). Zones 0, 1, 2, and 6 are always enabled.
B.
Each zone can be programmed with different wait states, setup and hold timing, and is supported by zone chip
selects (XZCS0AND1, XZCS2, XZCS6AND7), which toggle when an access to a particular zone is performed. These
features enable glueless connection to many external memories and peripherals.
C.
The chip selects for Zone 0 and Zone 1 are ANDed internally together to form one chip select (XZCS0AND1). Any
external memory that is connected to XZCS0AND1 is dually mapped to both Zone 0 and Zone 1.
D.
The chip selects for Zone 6 and Zone 7 are ANDed internally together to form one chip select (XZCS6AND7). Any
external memory that is connected to XZCS6AND7 is dually mapped to both Zone 6 and Zone 7. This means that if
Zone 7 is disabled (via the MP/MC mode), then any external memory is still accessible via Zone 6 address space.
E.
XCLKOUT is also pinned out on the F2810 and F2811 devices.
Figure 6-16. External Interface Block Diagram



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