TMS320F2810PBKA datasheet(140/173 Pages) TI

140 / 173 page

HSPCLK

PLL

X1/XCLKIN

Power

Modes

Control

Watchdog

Block

C28x CPU

High-Speed Peripherals

EV-A/B

High-Speed Prescaler

Low-Speed Prescaler

Clock Enables

System

Control

Registers

Peripheral

Registers

XF_XPLLDIS

ADC

Registers

12-Bit ADC

16 ADC Inputs

HSPCLK

LSPCLK

Peripheral Reset

SYSCLKOUT

XRS

Reset

GPIO

MUX

GPIOs

I/O

OSC

CLKIN

(A)

Low-Speed Peripherals

SCI-A/B, SPI, McBSP

Peripheral

Registers

eCAN

Peripheral

Registers

140

TMS320F2810, TMS320F2811, TMS320F2812

SPRS174U – APRIL 2001 – REVISED JULY 2019

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Product Folder Links: TMS320F2810 TMS320F2811 TMS320F2812

Detailed Description

6.8

System Control

This section describes the F281x oscillator, PLL and clocking mechanisms, the watchdog function and the

low-power modes. Figure 6-19 shows the various clock and reset domains in the F281x devices that will

be discussed.

CLKIN is the clock input to the CPU. SYSCLKOUT is the output clock of the CPU. They are of the same frequency.

Figure 6-19. Clock and Reset Domains

TMS320F2810PBKA Datasheet(PDF) 140 Page - Texas Instruments

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