TMS320F2810PBKA datasheet(144/173 Pages) TI

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(A)

X1/XCLKIN

Crystal

(a)

(b)

External Clock Signal

(Toggling 0-V

)

X1/XCLKIN

144

TMS320F2810, TMS320F2811, TMS320F2812

SPRS174U – APRIL 2001 – REVISED JULY 2019

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Detailed Description

6.10 PLL-Based Clock Module

The F281x has an on-chip, PLL-based clock module. This module provides all the necessary clocking

signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control to

select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR

131072 XCLKIN cycles.

The PLL-based clock module provides two modes of operation:

•

Crystal operation: This mode allows the use of an external crystal/resonator to provide the time base

to the device.

•

External clock source operation: This mode allows the internal oscillator to be bypassed. The device

clocks are generated from an external clock source input on the X1/XCLKIN pin.

TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the

DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also

advise the customer regarding the proper tank component values that will ensure start-up and stability over the entire

operating range.

Figure 6-21. Recommended Crystal/Clock Connection

Table 6-29. Possible PLL Configuration Modes

PLL MODE

REMARKS

SYSCLKOUT

PLL Disabled

Invoked by tying XPLLDIS pin low upon reset. PLL block is completely disabled.

Clock input to the CPU (CLKIN) is directly derived from the clock signal present at the

X1/XCLKIN pin.

XCLKIN

PLL Bypassed

Default PLL configuration upon power-up, if PLL is not disabled. The PLL itself is

bypassed. However, the /2 module in the PLL block divides the clock input at the

X1/XCLKIN pin by two before feeding it to the CPU.

XCLKIN/2

PLL Enabled

Achieved by writing a non-zero value “n” into PLLCR register. The /2 module in the

PLL block now divides the output of the PLL by two before feeding it to the CPU.

(XCLKIN * n) / 2

6.11 External Reference Oscillator Clock Option

The typical specifications for the external quartz crystal for a frequency of 30 MHz are listed below:

•

Fundamental mode, parallel resonant

•

CL (load capacitance) = 12 pF

•

CL1 = CL2 = 24 pF

•

Cshunt = 6 pF

•

ESR range = 25 to 40 Ω

TMS320F2810PBKA Datasheet(PDF) 144 Page - Texas Instruments

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