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TMS320F2810PBKA Datasheet(PDF) 146 Page - Texas Instruments |
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TMS320F2810PBKA Datasheet(HTML) 146 Page - Texas Instruments |
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146 / 173 page ![]() 146 TMS320F2810, TMS320F2811, TMS320F2812 SPRS174U – APRIL 2001 – REVISED JULY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: TMS320F2810 TMS320F2811 TMS320F2812 Detailed Description Copyright © 2001–2019, Texas Instruments Incorporated (1) The Exit column lists which signals or under what conditions the low-power mode will be exited. A low signal, on any of the signals, will exit the low-power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the IDLE mode will not be exited and the device will go back into the indicated low-power mode. (2) The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the core (SYSCLKOUT) is still functional; while on the 24x/240x, the clock is turned off. (3) On the C28x, the JTAG port can still function even if the core clock (CLKIN) is turned off. 6.13 Low-Power Modes Block The low-power modes on F281x are similar to the 240x devices. Table 6-30 summarizes the various modes. Table 6-30. Low-Power Modes MODE LPM[1:0] OSCCLK CLKIN SYSCLKOUT EXIT(1) Normal X,X on on on – IDLE 0,0 on on on(2) XRS, WDINT, Any Enabled Interrupt, XNMI, Debugger(3) STANDBY 0,1 on (watchdog still running) off off XRS, WDINT, XINT1, XNMI, T1/2/3/4CTRIP, C1/2/3/4/5/6TRIP, SCIRXDA, SCIRXDB, CANRX, Debugger(3) HALT 1,X off (oscillator and PLL turned off, watchdog not functional) off off XRS, XNMI, Debugger(3) The various low-power modes operate as follows: IDLE Mode This mode is exited by any enabled interrupt or an XNMI that is recognized by the processor. The LPM block performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0. STANDBY Mode All other signals (including XNMI) will wake the device from STANDBY mode if selected by the LPMCR1 register. The user will need to select which signal(s) will wake the device. The selected signal(s) are also qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the LPMCR0 register. HALT Mode Only the XRS and XNMI external signals can wake the device from HALT mode. The XNMI input to the core has an enable/disable bit. Hence, it is safe to use the XNMI signal for this function. NOTE The low-power modes do not affect the state of the output pins (PWM pins included). They will be in whatever state the code left them when the IDLE instruction was executed. |
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