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TMS320F2810PBKA Datasheet(PDF) 145 Page - Texas Instruments |
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TMS320F2810PBKA Datasheet(HTML) 145 Page - Texas Instruments |
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145 / 173 page  /512 OSCCLK WDCR (WDPS[2:0]) WDCLK WDCNTR[7:0] Good Key Bad Key 1 0 1 WDCR (WDCHK[2:0]) Bad WDCHK Key WDCR (WDDIS) Clear Counter SCSR (WDENINT) Watchdog Prescaler Generate Output Pulse (512 OSCCLKs) 8-Bit Watchdog Counter CLR WDRST WDINT Core-reset WDRST (A) XRS Internal Pullup WDKEY[7:0] Watchdog 55 + AA Key Detector 145 TMS320F2810, TMS320F2811, TMS320F2812 www.ti.com SPRS174U – APRIL 2001 – REVISED JULY 2019 Submit Documentation Feedback Product Folder Links: TMS320F2810 TMS320F2811 TMS320F2812 Detailed Description Copyright © 2001–2019, Texas Instruments Incorporated 6.12 Watchdog Block The watchdog block on the F281x is identical to the one used on the 240x devices. The watchdog module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter has reached its maximum value. To prevent this, the user disables the counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset the watchdog counter. Figure 6-22 shows the various functional blocks within the watchdog module. A. The WDRST signal is driven low for 512 OSCCLK cycles. Figure 6-22. Watchdog Module The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode timer. In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is the watchdog. The WATCHDOG module will run off the PLL clock or the oscillator clock. The WDINT signal is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See Section 6.13, Low-Power Modes Block, for more details. In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of IDLE mode. In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence, so is the WATCHDOG. |
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