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DP83936AVF Datasheet(PDF) 41 Page - National Semiconductor (TI) |
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DP83936AVF Datasheet(HTML) 41 Page - National Semiconductor (TI) |
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41 / 104 page  60 SONIC-T Registers (Continued) 642 Data Configuration Register (RAk50l e 1h) This register (Figure 6-5) establishes the bus cycle options for readingwriting data tofrom 16- or 32-bit memory systems During a hardware reset bits 15 and 13 are cleared all other bits are unaffected (Because of this the first thing the driver software does to the SONIC-T should be to set up this register) All bits are unaffected by a software reset This register must only be accessed when the SONIC-T is in reset mode (ie the RST bit is set in the Command register) 15 14 13 12 11 10 9876543210 EXBUS 0 LBR PO1 PO0 SBUS USR1 USR0 WC1 WC0 DW BMS RFT1 RFT0 TFT1 TFT0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw r e read only rwereadwrite FIGURE 6-5 Data Configuration Register Field Meaning EXBUS EXTENDED BUS MODE LBR LATCHED BUS RETRY PO0PO1 PROGRAMMABLE OUTPUTS SBUS SYNCHRONOUS BUS MODE USR0 USR1 USER DEFINABLE PINS WC0 WC1 WAIT STATE CONTROL DW DATA WIDTH SELECT BMS BLOCK MODE SELECT FOR DMA RFT0 RFT1 RECEIVE FIFO THRESHOLD TFT0 TFT1 TRANSMIT FIFO THRESHOLD Bit Description 15 EXBUS EXTENDED BUS MODE Setting this bit enables the Extended Bus mode which enables the following 1 Extended Programmable Outputs EXUSR k30l This changes the TXD LBK RXC and RXD pins from the external ENDEC interface into four programmable user outputs EXUSR k30l respectively which are similar to USR k10l These outputs are programed with bits 15-12 in the DCR2 (see Section 647) On hardware reset these four pins will be TRI-STATE and will remain that way until the DCR is changed If EXBUS is enabled then these pins will remain TRI-STATE until the SONIC-T becomes a bus master at which time they will be driven according to the DCR2 If EXBUS is disabled then these four pins work normally as external ENDEC interface pins 2 Synchronous Termination STERM This changes the TXC pin from the External ENDEC interface into a synchronous memory termination input for compatibility with Motorola style processors This input is only useful when Asynchronous Bus mode is selected (bit 10 below is set to ‘‘0’’) and the Bus Mode is set to Motorola Mode (BMODE e 1) On hardware reset this pin will be TRI-STATE and will remain that way until the DCR is changed If EXBUS is enabled this pin will remain TRI-STATE until the SONIC-T becomes a bus master at which time it will become the STERM input If EXBUS is disabled then this pin works normally as the TXC pin for the external ENDEC interface 3 Asynchronous Bus Retry Causes BRT to be clocked in asynchronously off the falling edge of bus clock This only applies however when the SONIC-T is operating in asynchronous mode (bit 10 below is set to ‘‘0’’) If EXBUS is not set XTO (BRT) is sampled synchronously off the rising edge of bus clock 14 Must be 0 13 LBR LATCHED BUS RETRY The LBR bit controls the mode of operation of the BRT signal (see pin description Section 20) It allows the BUS Retry operation to be latched or unlatched 0 Unlatched mode The assertion of BRT forces the SONIC-T to finish the current DMA operation and get off the bus The SONIC-T will retry the operation when BRT is deasserted 1 Latched mode The assertion of BRT forces the SONIC-T to finish the current DMA operation as above however the SONIC-T will not retry until BRT is deasserted and the BR bit in the ISR (see Section 646) has been reset and BRT is deasserted Hence the mode has been latched on until the BR bit is cleared Note Unless LBR is set to a ‘‘1’’ BRT must remain asserted at least until the SONIC-T has gone idle See sec 736 12 11 PO1PO0 PROGRAMMABLE OUTPUTS The PO1PO0 bits individually control the USR10 pins respectively when SONIC-T is a bus master (HLDA or BGACK is active) When PO1PO0 are set to a 1 the USR1USR0 pins are high during bus master operations and when these bits are set to a 0 the USR1USR0 pins are low during bus master operations http www nationalcom 41 |
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