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DP83936AVF Datasheet(PDF) 82 Page - National Semiconductor (TI) |
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DP83936AVF Datasheet(HTML) 82 Page - National Semiconductor (TI) |
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82 / 104 page  90 AC and DC Specifications (Continued) MEMORY READ BMODE e 0 ASYNCHRONOUS MODE TLF12597 – 63 Number Parameter 20 MHz 25 MHz 33 MHz Units Min Max Min Max Min Max T9 BSCK to Address ValidHold Time 3 26 3 24 3 22 ns T11 BSCK to ADS Low 26 24 22 ns T11b BSCK to ECS Low 19 17 15 ns T11d BSCK to DS Low 17 15 13 ns T12 BSCK to ADS High 24 22 20 ns T12b BSCK to ECS High 29 27 25 ns T12d BSCK to DS High 17 15 13 ns T15 ADS High Width 45 35 25 ns T16 Read Data Strobe High Width 45 35 25 ns T17 Read Data Strobe Low Width 40 30 20 ns T23 Read Data Setup Time to BSCK 6 5 4 ns T24 Read Data Hold Time from BSCK 5 5 5 ns T28 BSCK to MWR (Read) Valid (Note 1) 26 24 22 ns T32a RDYi Asynchronous Setup Time to BSCK (Note 2) 5 4 3 ns T33a RDYi Asynchronous Hold Time to BSCK 5 5 5 ns Note 1 For successive read operations MWR remains low Note 2 This setup time assures that the SONIC-T terminates the memory cycle on the next bus clock (BSCK) RDYi does not need to be synchronized to the bus clock though since it is an asynchronous input in this case RDYi is sampled during the falling edge of BSCK If the SONIC-T samples RDYi low during the T1 cycle the SONIC-T will finish the current access in a total of two bus clocks instead of three which would be the case if RDYi had been sampled low during T2 (wait) (This is assuming that programmable wait states are set to 0) http www nationalcom 82 |
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