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DP83936AVF Datasheet(PDF) 45 Page - National Semiconductor (TI) |
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DP83936AVF Datasheet(HTML) 45 Page - National Semiconductor (TI) |
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45 / 104 page  60 SONIC-T Registers (Continued) 644 Transmit Control Register (RAk50l e 3h) This register is used to program the SONIC-T’s transmit actions and provide status information after a packet has been transmitted (Figure 6-7) At the beginning of transmission bits 15 14 13 and 12 from the TXpktconfig field are loaded into the TCR to configure the various transmit modes (see Section 5511) When the transmission ends bits 10 – 0 indicate status information and are set to a ‘‘1’’ when the corresponding condition is true These bits along with the number of collisions information are written into the TXpktstatus field at the end of transmission (see Section 5512) Bits 9 and 5 are cleared after the TXpktstatus field has been written Bits 10 7 6 and 1 are cleared at the commencement of the next transmission while bit 8 is set at this time A hardware reset sets bits 8 and 0 to a ‘‘1’’ and bit 1 to a ‘‘0’’ This register is unaffected by a software reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PINT POWC CRCI EXDIS 0 EXD DEF NCRS CRSL EXC OWC 0 PMB FU BCM PTX rw rw rw rw r r r r r r r r r r r r reread only rwereadwrite FIGURE 6-7 Transmit Control Register Field Meaning PINT PROGRAMMABLE INTERRUPT POWC PROGRAMMED OUT OF WINDOW COLLISION TIMER CRCI CRC INHIBIT EXDIS DISABLE EXCESSIVE DEFERRAL TIMER EXD EXCESSIVE DEFERRAL DEF DEFERRED TRANSMISSION NCRS NO CRS CRSL CRS LOST EXC EXCESSIVE COLLISIONS OWC OUT OF WINDOW COLLISION PMB PACKET MONITORED BAD FU FIFO UNDERRUN BCM BYTE COUNT MISMATCH PTX PACKET TRANSMITTED OK Bit Description 15 PINTR PROGRAMMABLE INTERRUPT This bit allows transmit interrupts to be generated under software control The SONIC-T will issue an interrupt (PINT in the Interrupt Status Register) immediately after reading a TDA and detecting that PINT is set in the TXpktconfig field Note In order for PINT to operate properly it must be set and reset in the TXpktconfig field by alternating TDAs This is necessary because after PINT has been issued in the ISR PINT in the Transmit Control Register must be cleared before it is set again in order to have the interrupt issued for another packet The only effective way to do this is to set PINT toa1no more often than every other packet 14 POWC PROGRAM ‘‘OUT OF WINDOW COLLISION’’ TIMER This bit programs when the out of window collision timer begins 0 timer begins after the Start of Frame Delimiter (SFD) 1 timer begins after the first bit of preamble 13 CRCI CRC INHIBIT 0 transmit packet with 4-byte FCS field 1 transmit packet without 4-byte FCS field 12 EXDIS DISABLE EXCESSIVE DEFERRAL TIMER 0 excessive deferral timer enabled 1 excessive deferral timer disabled 11 Must be 0 10 EXD EXCESSIVE DEFERRAL Indicates that the SONIC-T has been deferring for 32 ms The transmission is aborted if the excessive deferral timer is enabled (ie EXDIS is reset) This bit can only be set if the excessive deferral timer is enabled http www nationalcom 45 |
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