 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DP83936AVF Datasheet(PDF) 92 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
DP83936AVF Datasheet(HTML) 92 Page - National Semiconductor (TI) |
|
|
92 / 104 page  90 AC and DC Specifications (Continued) REGISTER READ BMODE e 0 (Note 1) TLF12597 – 72 Number Parameter 20 MHz 25 MHz 33 MHz Units Min Max Min Max Min Max T56 CS Asynchronous Setup to BSCK (Notes 4 6) 8 7 6 ns T60a CS and SAS to SMACK Low (Notes 3 5 6) 0 4 0 4 0 4 bcyc T62 SAS Asynchronous Setup to BSCK (Notes 4 6) 7 6 5 ns T63 Register Address Setup Time to SAS 765 ns T64 Register Address Hold Time from SAS 876 ns T65 SAS Minimum Low Width (Notes 4 6) 20 17 15 ns T68 SWR (Read) Hold from SAS 876 ns T73 SWR (Read) Setup to SAS 765 ns T75 BSCK to RDYo Low 20 18 16 ns T76 SAS or CS to RDYo High (Note 2) 34 32 30 ns T79 SAS or CS to SMACK High (Note 2) 18 16 14 ns T81 BSCK to SMACK Low 22 20 18 ns T82 BSCK to Register Data Valid 44 42 40 ns T85 SAS or CS to Data TRI-STATE (Notes 2 7) 34 32 30 ns T85a Minimum CS Deassert Time (Note 3) 1 1 1 bcyc Note 1 This figure shows a slave access to the SONIC-T The BSCK states (T1 T2 etc) are the equivalent processor states during a slave access Note 2 If CS is deasserted before the falling edge of SAS T76 T79 and T85 are referenced from the rising edge of CS Note 3 bcyc e bus clock cycle time (T3) Note 4 It is not necessary to meet the setup time for CS (T56) and the setup time for SAS (T62) since these signals are asynchronously sampled Meeting these setup times for these signals however makes it possible to use T60a to determine exactly when SMACK will be asserted For multiple register accesses CS can be held low and SAS can be used to delimit the slave cycle In this case SMACK will be driven low by the SONIC-T after T60a when T62 is met T85a must be met to ensure proper slave operation once CS is deasserted Note 5 The smaller value for T60a refers to when the SONIC-T is accessed during an Idle condition and the other value refers to when the SONIC-T is accessed during non-idle conditions These values are not tested but are guaranteed by design Note 6 SAS may be asserted low anytime before or simultaneous to the falling edge of CS Register address and slave readwrite signals are latched on the rising edge of the SAS and if T62 is met SMACK will be asserted by the SONIC-T after T60a If T62 is not met SONIC-T will sample SAS again on the next falling edge of the clock and SMACK will not be asserted until SAS is deasserted Note 7 This timing value includes an RC delay inherent in the test measurement These signals typically TRI-STATE 7 ns earlier enabling other devices to drive these lines without contention http www nationalcom 92 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
