DP83936AVF datasheet(16/104 Pages) NSC

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30 Functional Description (Continued)

The ENDEC also provides both the receive and transmit

clocks to the MAC unit The transmit clock is one half of the

oscillator input and the receive clock is extracted from the

input data by the PLL

Oscillator

The oscillator generates the 10 MHz transmit

clock signal for network timing The oscillator is controlled

by a parallel resonant crystal or by an external clock (see

Section 813) The 20 MHz output of the oscillator is divided

by 2 to generate the 10 MHz transmit clock (TXC) for the

MAC section The oscillator also provides an internal clock

signal for the encoding and decoding circuits

Loopback Functions

The SONIC-T provides three loop-

back modes which allow for loopback testing at the MAC

ENDEC and external transceiver level (see Section 37 for

details) It is important to note that when the SONIC-T is

transmitting the transmitted packet will always be looped

back by the external transceiver The SONIC-T takes ad-

vantage of this to monitor the transmitted packet See the

explanation of the Receive State Machine in Section 331

for more information about monitoring transmitted packets

322 Selecting an External ENDEC

An option is provided on SONIC-T to disable the on-chip

ENDEC unit and use an external ENDEC The internal IEEE

8023 ENDEC can be bypassed by connecting the EXT pin

to VCC (EXTe1) In this mode the MAC signals are redirect-

ed out from the chip allowing an external ENDEC to be

used See Section 20 for the alternate pin definitions

33 MEDIA ACCESS CONTROL (MAC) UNIT

The Media Access Control (MAC) unit performs the control

functions for the media access of transmitting and receiving

packets over Twisted Pair or AUI During transmission the

MAC unit frames information from the transmit FIFO and

supplies serialized data to the ENDEC unit During recep-

tion the incoming information from the ENDEC unit is dese-

rialized the frame checked for valid reception and the data

is transferred to the receive FIFO Control and status regis-

ters on the SONIC-T govern the operation of the MAC unit

331 MAC Receive Section

The receive section

(Figure 3-6) controls the MAC receive

operations during reception loopback and transmission

During reception the deserializer goes active after detecting

the 2-bit Start of Frame Delimiter (SFD) pattern (see Section

41) It then frames the incoming bits into octet boundaries

and transfers the data to the 32-byte receive FIFO Concur-

rently the address comparator compares the Destination

Address Field to the addresses stored in the chip’s Content

Addressable Memory (CAM) address registers If a match

occurs the deserializer passes the remainder of the packet

to the receive FIFO The packet is decapsulated when the

carrier sense input pin (CRS) goes inactive At the end of

reception the receive section checks the following

Frame alignment errors

CRC errors

Length errors (runt packets)

The appropriate status is indicated in the Receive Control

ceive section operates the same as during normal recep-

tion

During transmission the receive section remains active to

allow monitoring of the self-received packet The Cyclic Re-

dundancy Code (CRC) checker operates as normal and the

Source Address field is compared with the CAM address

entries Status of the CRC check and the source address

comparison is indicated by the PMB bit in the Transmit Con-

trol register (see Section 644) No data is written to the

receive FIFO during transmit operations

The receive section consists of the following blocks detailed

below

Receive State Machine (RSM)

The RSM insures the prop-

er sequencing for normal reception and self-reception dur-

ing transmission When the network is inactive the RSM

remains in an idle state continually monitoring for network

activity If the network becomes active the RSM allows the

deserializer to write data into the receive FIFO During this

state the following conditions may prevent the complete

reception of the packet

FIFO OverrunThe receive FIFO has been completely

filled before the SONIC-T could buffer the data to mem-

ory

CAM Address MismatchThe packet is rejected be-

cause of a mismatch between the destination address of

the packet and the address in the CAM

Memory Resource ErrorThere are no more resources

(buffers or descriptors) available for buffering the incom-

ing packets

Collision or Other ErrorA collision occurred on the net-

work or some other error such as a CRC error occurred

(this is true if the SONIC-T has been told to reject pack-

ets on a collision or reject packets with errors)

If these conditions do not occur the RSM processes the

packet indicating the appropriate status in the Receive Con-

trol register

TLF12597 – 9

FIGURE 3-6 MAC Receiver

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