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DP83936AVF Datasheet(PDF) 99 Page - National Semiconductor (TI) |
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DP83936AVF Datasheet(HTML) 99 Page - National Semiconductor (TI) |
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99 / 104 page ![]() 90 AC and DC Specifications (Continued) ENDEC-MAC SERIAL TIMING FOR RECEPTION (EXTERNAL ENDEC MODE) TLF12597 – 79 Number Parameter Min Max Units T118 Receive Clock High Time 40 ns T119 Receive Clock Low Time 40 ns T120 Receive Clock Cycle Time 90 110 ns T121 RXD Setup to RXC 20 ns T122 RXD Hold from RXC 15 ns T124 Maximum Allowed Dribble Bits 6 Bits T125 Receive Recovery Time (Note 2) T126 RXC to Carrier Sense Low (Notes 1 3) 1 rcyc Note 1 tcyc e transmit clocks rcyc e receive clocks bcyc e T3 Note 2 This parameter refers to longest time (not including wait-states) the SONICTM requires to perform its end of receive processing and be ready for the next start of frame delimiter This time is 4 a 36 ccyc bcyc This is guaranteed by design and is not tested Note 3 To ensure proper receive operation a minimum of 5 RXCs after CRS low are required ENDEC-MAC SERIAL TIMING FOR TRANSMIT (NO COLLISION) TLF12597 – 80 Number Parameter Min Max Units T127 Transmit Clock High Time 40 ns T128 Transmit Clock Low Time 40 ns T129 Transmit Clock Cycle Time 90 110 ns T130 TXC to TXE High 40 ns T131 TXC to TXD Valid 40 ns T132 TXD Hold Time from TXC 0 ns T133 TXC to TXE Low 40 ns T134 TXE Low to Start of CD Heartbeat (Note 1) 64 tcyc T135 Collision Detect Width (Note 1) 2 tcyc Note 1 tcyc e transmit clock http www nationalcom 99 |
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