DP83936AVF datasheet(103/104 Pages) NSC

103 / 104 page

100 AC Timing Test Conditions

All specifications are valid only if the mandatory isolation is

employed and all differential signals are taken to be at the

AUI side of the pulse transformer

Input Pulse Levels (TTLCMOS)

GND to 30V

Input Rise and Fall Times (TTLCMOS)

5 ns

Input and Output Reference

Levels (TTLCMOS)

15V

Input Pulse Levels (Diff)

350 mV to b1315 mV

Input and Output

50% Point of

Reference Levels (Diff)

the Differential

TRI-STATE Reference Levels

Float (DV) g05V

OUTPUT LOAD

(See Figure below)

TLF12597 – 86

Note 1

50 pF includes scope and jig capacitance

Note 2

S1 e Open for timing test for push pull outputs

S1 e VCC for VOL test

S1 e GND for VOH test

S1 e VCC for High Impedance to active low and active low to High

Impedance measurements

S1 e GND for High Impedance to active high and active High to

High Impedance measurements

Pin Capacitance TA e 25 C f e 1 MHz

Symbol

Parameter

Typ

Units

CIN

Input Capacitance

COUT

Output Capacitance

DERATING FACTOR

Output timing is measured with a purely capacitive load of

50 pF The following correction factor can be used for other

loads CL t 50 pF e 005 nspF

AUI Transmit Test Load

TLF12597 – 87

Note

In the above diagram the TXa and TXb signals are taken from the

AUI side of the isolation (pulse transformer) The pulse transformer

used for all testing is a 100 mH g01% Pulse Engineering PE64103

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DP83936AVF Datasheet(PDF) 103 Page - National Semiconductor (TI)

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