DP83936AVF datasheet(10/104 Pages) NSC

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20 Pin Description (Continued)

TABLE 2-1 Pin Description

(Continued)

Symbol

Driver

Direction

Description

Type

BUS INTERFACE PINS (MOTOROLA MODE BMODE e 1)

TRI

O Z

ADDRESS STROBE (AS)

The falling edge indicates valid status and address The rising edge

indicates the termination of the memory cycle

MRW

TRI

O Z

MEMORY READWRITE STROBE (MRW)

When the SONIC-T has acquired the bus this signal

indicates the direction of the data transfer This signal is high during a read cycle and low during a

write cycle

INT

O Z

INTERRUPT (INT)

Indicates that an interrupt (if enabled) is pending from one of the sources

indicated by the Interrupt Status register Interrupts that are disabled in the Interrupt Mask

O Z

BUS REQUEST (BR)

The SONIC-T asserts this pin low when it attempts to gain access to the

bus When inactive this signal is at TRI-STATE

BUS GRANT (BG)

This signal is a bus grant The system asserts this pin low to indicate potential

mastership of the bus

BGACK

TRI

O Z

BUS GRANT ACKNOWLEDGE

The SONIC-T asserts this pin low when it has determined that it

can gain ownership of the bus The SONIC-T checks the following conditions before driving

BGACK

1 BG has been received through the bus arbitration process

2 AS is deasserted indicating that the previous master has finished using the bus

3 DSACK0 and DSACK1 are deasserted indicating that the previous slave device is off the bus

4 BGACK is deasserted indicating that the previous master is off the bus

SRW

SLAVE READWRITE (SRW)

The system asserts this pin to indicate whether it will read from or

write to the SONIC-T’s registers This signal is asserted high during a read and low during a write

DSACK0

TRI

I O Z

DATA AND SIZE ACKNOWLEDGE 0 AND 1 (DSACK01 BMODE e 1)

These pins are the

output slave acknowledge to the system when the SONIC-T registers have been accessed and

DSACK1

TRI

I O Z

the input slave acknowledgement when the SONIC-T is busmaster When a register has been

accessed the SONIC-T drives both DSACK0 and DSACK1 pins low to terminate the slave cycle

(Note that the SONIC-T responds as a 32-bit peripheral by driving both DSACK0 and DSACK1

low but drives data only on lines D0 – D15 Lines D16 – D32 are driven but invalid)

When the SONIC-T is bus master it samples these pins before terminating its memory cycle

When SONIC-T is in 32-bit bus master mode both DSACK0 and DSACK1 must be asserted to

terminate the cycle However if the SONIC-T is in 16-bit bus master mode only the assertion of

DSACK1 is required to terminate the cycle These pins are sampled synchronously or

asynchronously depending on the state of the SBUS bit in the Data Configuration register (See

Section 735 for details) Note that the SONIC-T does not allow dynamic bus sizing Bus size is

statically defined in the Data Configuration register (see Section 642)

USER DEFINABLE PINS

USR01

TRI

I O Z

USER DEFINE 01

These signals are inputs when the SONIC-T is hardware reset and are

outputs when the SONIC-T is a bus master (HLDA or BGACK asserted) When hard reset (RST)

is low these signals input directly into bits 8 and 9 of the Data Configuration Register (DCR)

respectively The levels on these pins are latched on the rising edge of RST During busmaster

operations (HLDA or BGACK is active) these pins are outputs whose levels are programmable

through bits 11 and 12 of the DCR respectively The USR01 pins should be pulled up to VCC or

pulled down to ground A 47 kX pull-up resistor is recommended

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DP83936AVF Datasheet(PDF) 10 Page - National Semiconductor (TI)

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