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DP83936AVF Datasheet(PDF) 46 Page - National Semiconductor (TI) |
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DP83936AVF Datasheet(HTML) 46 Page - National Semiconductor (TI) |
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46 / 104 page ![]() 60 SONIC-T Registers (Continued) 644 Transmit Control Register (Continued) Bit Description 9 DEF DEFERRED TRANSMISSION Indicates that the SONIC-T has deferred its transmission during the first attempt If subsequent collisions occur this bit is reset This bit is cleared after the TXpktstatus field is written in the TDA 8 NCRS NO CRS Indicates that Carrier Sense (CRS) was not present during transmission CRS is monitored from the beginning of the Start of Frame Delimiter to the last byte transmitted The transmission will not be aborted This bit is set at the start of preamble and is reset if CRS is detected Hence if CRS is never detected throughout the entire transmission of the packet this bit will remain set Note NCRS will always remain set in MAC loopback as long as there is no activity on the RXg 7 CRSL CRS LOST Indicates that CRS has gone low or has not been present during transmission CRS is monitored from the beginning of the Start of Frame Delimiter to the last byte transmitted The transmission will not be aborted Note if CRS was never present both NCRS and CRSL will be set simultaneously Also CRSL will always be set in MAC loopback 6 EXC EXCESSIVE COLLISIONS Indicates that 16 collisions have occurred The transmission is aborted 5 OWC OUT OF WINDOW COLLISION Indicates that an illegal collision has occurred after 512 ms (one slot time) from either the first bit of preamble or from SFD depending upon the POWC bit The transmission backs off as in a normal transmission This bit is cleared after the TXpktstatus field is written in the TDA 4 Must be 0 3 PMB PACKET MONITORED BAD This bit is set if after the receive unit has monitored the transmitted packet the CRC has been calculated as invalid as a result of a Frame Alignment error or the Source Address does not match any of the CAM address registers Note 1 The SONIC-T’s CRC checker is active during transmission Note 2 If CRC has been inhibited for transmissions (CRCI is set) this bit will always be low This is true regardless of Frame Alignment or Source Address mismatch errors Note 3 If a Receive FIFO overrun has occurred the transmitted packet is not monitored completely Thus if PMB is set along with the RFO bit in the ISR then PMB has no meaning The packet must be completely received before PMB has meaning Note 4 This bit is always zero in loopback mode (True for all three types of looback mode) 2 FU FIFO UNDERRUN Indicates that the SONIC-T has not been able to access the bus before the FIFO has emptied This condition occurs from excessive bus latency andor slow bus clock The transmission is aborted (See Section 352) 1 BCM BYTE COUNT MISMATCH This bit is set when the SONIC-T detects that the TXpktpkt size field is not equal to the sum of the TXpktfrag size field(s) Transmission is aborted This bit will also be set when Excessive Collisions (bit 6 of the transmit control register) occur during transmission 0 PTX PACKET TRANSMITTED OK Indicates that a packet has been transmitted without the following errors Excessive Collisions (EXC) Excessive Deferral (EXD) FIFO Underrun (FU) Byte Count Mismatch (BCM) http www nationalcom 46 |
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