DP83936AVF datasheet(8/104 Pages) NSC

8 / 104 page

20 Pin Description (Continued)

TABLE 2-1 Pin Description

(Continued)

Symbol

Driver

Direction

Description

Type

NETWORK INTERFACE PINS

(Continued)

OSCIN

CRYSTAL FEEDBACK INPUT OR EXTERNAL OSCILLATOR INPUT

This signal is used to

provide clocking signals for the internal ENDEC A crystal may be connected to this pin along

with OSCOUT or an oscillator module may be used See Section 813 for more information

about using an oscillator or crystal

OSCOUT

CRYSTAL FEEDBACK OUTPUT

This signal is used to provide clocking signals for the internal

ENDEC A crystal can be connected to this pin along with OSCIN See Section 813 for more

information about using an oscillator or crystal

BUS INTERFACE PINS (BOTH BUS MODES)

BMODE

BUS MODE

This input enables the SONIC-T to be compatible with standard microprocessor

buses The level of this pin affects byte ordering (little or big endian) and controls the operation

of the bus interface control signals A high level (tied to VCC) selects Motorola mode (big

endian) and a low level (tied to ground) selects NationalIntel mode (little endian) Note the

alternate pin definitions for AS ADS MRW MWR INT INT BR HOLD BG HLDA SRW SWR

DSACK0 RDYo and DSACK1RDYi (See Sections 731 734 and 735 for bus interface

information)

D31 – D0

TRI

I O Z

DATA BUS

These bidirectional lines are used to transfer data on the system bus When the

SONIC-T is a bus master 16-bit data is transferred on D15 – D0 and 32-bit data is transferred on

D31 – D0 When the SONIC-T is accessed as a slave register data is driven onto line D15 – D0

D31 – D16 are held TRI-STATE

A31 – A1

TRI

O Z

ADDRESS BUS

These signals are used by the SONIC-T to drive the DMA address after the

SONIC-T has acquired the bus Since the SONIC-T aligns data to word boundaries only 31

address lines are needed

RA5 – RA0

These signals are used to access SONIC-T’s internal registers

When the SONIC-T is accessed the CPU drives these lines to select the desired SONIC-T

RESET

This signal is used to hardware reset the SONIC-T When asserted low the SONIC-T

transitions into the reset state after 10 transmit clocks or 10 bus clocks if the bus clock period is

greater than the transmit clock period

S2–S0

BUS STATUS

These three signals provide a continuous status of the current SONIC-T bus

operations See Section 733 for status definitions

BSCK

BUS CLOCK

This clock provides the timing for the SONIC-T DMA engine

CHIP SELECT

The system asserts this pin low to access the SONIC-T’s registers The

registers are selected by placing an address on lines RA5 – RA0

Note

Both CS and MREQ must not be asserted concurrently If these signals are successively

asserted there must be at least two bus clocks between the deasserting edge of the first signal

and the asserting edge of the second signal

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