DP83936AVF datasheet(65/104 Pages) NSC

Part #	DP83936AVF

Description	Full Duplex SONICTM-T Systems-Oriented Network Interface Controller with Twisted Pair Interface

PDF	104 Pages

Scroll/Zoom	100%

Manufacturer	NSC [National Semiconductor (TI)]

Direct Link	http://www.national.com

Logo

65 / 104 page

70 Bus Interface (Continued)

7354 Memory Cycle for BMODE e 0

Synchronous Mode

On the rising edge of T1 the SONIC-T asserts ADS and

ECS to indicate that the memory cycle is starting The ad-

dress (A31 – A1) bus status (S2 – S0) and the direction

strobe (MWR) are driven and do not change for the remain-

der of the memory cycle On the falling edge of T1 the

SONIC-T deasserts ECS ADS is deasserted on the rising

edge of T2

In Synchronous mode RDYi is sampled on the rising edge

at the end of T2 (the rising edge of the next T1) T2 states

will be repeated until RDYi is sampled properly In a low

state RDYi must meet the setup and hold times with respect

to the rising edge of bus clock for proper operation

During read cycles

(Figure 7-12) data (D31 – D0) is latched

at the rising edge at the end of T2 For write cycles

(Figure

7-13) data is driven on the falling edge of T1 and stays

driven until the end of the cycle

TLF12597 – 39

FIGURE 7-12 Memory Read BMODE e 0 Synchronous (1 Wait-State)

TLF12597 – 40

FIGURE 7-13 Memory Write BMODE e 0 Synchronous (1 Wait-State)

http

www nationalcom

DP83936AVF Datasheet(PDF) 65 Page - National Semiconductor (TI)