DP83936AVF datasheet(60/104 Pages) NSC

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70 Bus Interface (Continued)

7331 Bus Status Transitions

When the SONIC-T acquires the bus it only transfers data

tofrom a single area in memory (ie TDA TBA RDA RBA

RRA or CDA) Thus the bus status pins remain stable for

the duration of the block transfer cycle with the following

three exceptions 1) if the SONIC-T is accessed during a

block transfer S2 – S0 indicates bus idle during the register

access

then returns to the previous status

2) if the

SONIC-T finishes writing the Source Address during a block

transfer S2 – S0 changes from 010 to 011 or 3) during

an RDA access between the RXpktseq

no and RXpktlink

access and between the RXpktlink and RXpktin

use ac-

cess S2 – S0 will respectively indicate idle 111 for2or1

bus clocks Status will be valid on the falling edge of AS or

rising edge of ADS

Figure 7-5 illustrates the SONIC-T’s transitions through

memory during the process of transmission and reception

During transmission the SONIC-T reads the descriptor in-

formation from the TDA and then transmits data of the

packet from the TBA The SONIC-T moves back and forth

between the TDA and TBA until all fragments and packets

are transmitted During reception the SONIC-T takes one of

two paths In the first case (path A) when the SONIC-T

detects EOL e 0 from the previous reception it buffers the

accepted packet into the RBA and then writes the descrip-

tor information to the RDA If the RBA becomes depleted

(ie

RBWC01 k EOBC) it moves to the RRA to read a

resource descriptor In the second case (path B) when the

SONIC-T detects EOL e 1 from the previous reception it

rereads the RXpktlink field to determine if the system has

reset the EOL bit since the last reception If it has the

SONIC-T buffers the packet as in the first case Otherwise

it rejects the packet and returns to idle

734 Bus Mode Compatibility

For compatibility with different microprocessor and bus ar-

chitectures the SONIC-T operates in one of two modes (set

by the BMODE pin) called the NationalIntel or little endian

mode (BMODE tied low) and the Motorola or big endian

mode (BMODE tied high) The definitions for several pins

change depending on the mode the SONIC-T is in Table

7-2 shows these changes These modes affect both master

and slave bus operations with the SONIC-T

TABLE 7-2 Bus Mode Compatibility

Pin Name

BMODE e 0

BMODE e 1

(NationalIntel)

(Motorola)

BR HOLD

HOLD

BG HLDA

HLDA

MRW MWR

MWR

MRW

SRW SWR

SWR

SRW

DSACK0 RDYi

RDYi

DSACK0

DSACK1 RDYo

RDYo

DSACK1

AS ADS

ADS

INT INT

INT

TLF12597 – 32

FIGURE 7-5 Bus Status Transitions

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