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DP83936AVF Datasheet(PDF) 90 Page - National Semiconductor (TI) |
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DP83936AVF Datasheet(HTML) 90 Page - National Semiconductor (TI) |
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90 / 104 page ![]() 90 AC and DC Specifications (Continued) BUS RETRY TLF12597 – 70 Number Parameter 20 MHz 25 MHz 33 MHz Units Min Max Min Max Min Max T41 Bus Retry Synchronous Setup Time to BSCK 543 ns (Note 3) T41a Bus Retry Asynchronous Setup Time 654 ns to BSCK (Note 3) T42 Bus Retry Hold Time from BSCK (Note 2) 7 6 5 ns Note 1 Depending upon the mode the SONIC-T will assert and deassert HOLD from the rising or falling edge of BSCK Note 2 Unless Latched Bus Retry mode is set (LBR in the Data Configuration Register Section 432) BRT must remain asserted until after the Th state If Latched Bus Retry mode is used BRT does not need to satisfy T42 Note 3 T41 is for synchronous bus retry and T41a is for asynchronous bus retry (see Section 432 bit 15 Extended Bus Mode) Since T41a is an asynchronous setup time it is not necessary to meet it but doing so will guarantee that the bus exception occurs in the current memory transfer not the next http www nationalcom 90 |
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