DP83936AVF datasheet(7/104 Pages) NSC

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20 Pin Description (Continued)

TABLE 2-1 Pin Description

(Continued)

Symbol

Driver

Direction

Description

Type

NETWORK INTERFACE PINS

(Continued)

TXD

This pin will be TRI-STATE until the DCR has been written to (See Section 642 EXBUS for

more information)

EXUSR3

TRI

O Z

TRANSMIT DATA (TXD)

The serial NRZ data from the MAC unit which is to be decoded by an

external ENDEC Data is valid on the rising edge of TXC Although this signal is used internally by

the SONIC-T it is also provided as an output to the user

EXTENDED USER OUTPUT (EXUSR3)

When EXBUS has been set (see Section 642) this pin

becomes a programmable output It will remain TRI-STATE until the SONIC-T becomes a bus

master at which time it will be driven according to the value programmed in the DCR2 (see

Section 647)

TXE

TRANSMIT ENABLE

This pin is driven high when the SONIC-T begins transmission and remains

active until the last byte is transmitted Although this signal is used internally by the SONIC-T it is

also provided as an output to the user

TXCo

TRI

O Z

This pin will be TRI-STATE until the DCR has been written to (See Section 642

TXCi

EXBUS for more information)

STERM

TRANSMIT CLOCK OUTPUT (TXCo)

from the internal ENDEC (EXT e 0) This 10 MHz transmit

clock output is derived from the 20 MHz oscillator input When EXT e 0 the TXCo signal is

internally connected between the ENDEC and MAC units Although this signal is used internally

by the SONIC-T it is also provided as an output to the user

TRANSMIT CLOCK INPUT (TXCi)

from an external ENDEC (EXT e 1) This input clock from an

external ENDEC is used for shifting data out of the MAC unit serializer This clock is nominally

10 MHz

SYNCHRONOUS TERMINATION (STERM)

When the SONIC-T is a bus master it samples this

pin before terminating its memory cycle This pin is sampled synchronously and may only be used

in asynchronous bus mode when BMODE e 1 (See Section 735 for more details)

LBK

This pin will be TRI-STATE until the DCR has been written to (See Section 642 EXBUS for

more information)

EXUSR2

TRI

O Z

LOOPBACK (LBK)

When ENDEC Loopback mode is enabled LBK is asserted high Although

this signal is used internally by the SONIC-T it is also provided as an output to the user

EXTENDED USER OUTPUT (EXUSR2)

When EXBUS has been set (see Section 642) this pin

becomes a programmable output It will remain TRI-STATE until the SONIC-T becomes a bus

master at which time it will be driven according to the value programmed in the DCR2 (see

Section 647)

PCOMP

TRI

O Z

PACKET COMPRESSION

This pin is used with the Management Bus of the DP83950 Repeater

Interface Controller (RIC) The SONIC-T can be programmed to assert PCOMP whenever there is

a CAM match or when there is not a match The RIC uses this signal to compress (shorten) a

received packet for management purposes and to reduce memory usage (See the DP83950

datasheet for more details on the RIC Management Bus) The operation of this pin is controlled

by bits 1 and 2 in the DCR2 register PCOMP will remain TRI-STATE until these bits are written to

This signal is asserted right after the 4th bit of the 7th byte of the incoming packet and is

deasserted one transmit clock (TXC) after CSR is driven low

PREJ

PACKET REJECT

This signal is used to reject received packets When asserted low for at least

two receive clock cycles (RXC) the SONIC-T will reject the incoming packet This pin can be

asserted up to the 2nd to the last bit of reception to reject a packet

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DP83936AVF Datasheet(PDF) 7 Page - National Semiconductor (TI)

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