DP83936AVF datasheet(55/104 Pages) NSC

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60 SONIC-T Registers (Continued)

6412 General Purpose Timer

The SONIC-T contains a 32-bit general-purpose Watchdog

Timer for timing user-definable events

(Figure 6-14) This

timer is accessed by the user through two 16-bit readwrite

registers (WT1 and WT0) The lower count value is pro-

grammed through the WT0 register and the upper count

value is programmed through the WT1 register

These two registers are concatenated together to form the

complete 32-bit timer This timer clocked at

the Transmit

Clock (TXC) frequency counts down from its programmed

value and generates an interrupt if it is enabled Interrupt

Mask register when it rolls over from 0000 0000h to FFFF

FFFFh When the counter rolls over it continues decrement-

ing unless explicitly stopped (setting the STP bit) The timer

is controlled by the ST (Start Timer) and STP (Stop Timer)

bits in the Command register A hardware or software reset

halts but does not clear the General Purpose timer

WT1 (Upper Count Value)

WT0 (Lower Count Value)

FIGURE 6-14 Watchdog Timer Register

6413 Silicon Revision Register

This is a 16-bit read only register It contains information on

the current revision of the SONIC-T The DP83936AVUL re-

vision register is 0201h

70 Bus Interface

SONIC-T features a high speed non-multiplexed address

and data bus designed for a wide range of system environ-

ments The data bus can be programmed (via the Data Con-

figuration Register) to a width of either 32- or 16-bits

SONIC-T contains an on-chip DMA and supplies all the nec-

essary signals for DMA operation With 31 address lines

SONIC-T can access a full 2 G-word address space To

accommodate different memory speeds wait states can be

added to the bus cycle by two methods The memory sub-

system can add wait states by simply withholding the appro-

priate handshake signals or the SONIC-T can be pro-

grammed (via the Data Configuration Register) to add wait

states

The SONIC-T is designed to interface to both the National

Intel and Motorola style buses To facilitate minimum chip

count designs and complete bus compatibility the user can

program the SONIC-T for the following bus modes

NationalIntel bus operating in synchronous mode

NationalIntel bus operating in asynchronous mode

Motorola bus operating in synchronous mode

Motorola bus operating in asynchronous mode

The Bus Mode pin (BMODE) along with the SBUS bit in the

Data Configuration Register are used to select the bus

mode

This section illustrates some SONIC-T system interface ex-

amples and describes the various SONIC-T bus operations

71 PIN CONFIGURATIONS

There are two user selectable pin configurations for

SONIC-T to provide the proper interface signals for either

the NationalIntel or Motorola style buses The state of the

BMODE pin is used to define the pin configuration Section

10 shows the pin configurations for both NationalIntel

Mode (BMODE e 0 tied to ground) and Motorola Mode

(BMODE e 1 tied to VCC)

72 SYSTEM CONFIGURATION

Any device that meets the SONIC-T interface protocol and

electrical requirements (timing threshold and loading) can

be interfaced to SONIC-T Since two bus protocols are pro-

vided via the BMODE pin the SONIC-T can interface di-

rectly to most microprocessors

Figure 7-1 shows a typical

interface to the NationalIntel style bus (BMODE e 0) and

Figure 7-2 shows a typical interface to the Motorola style

bus (BMODE e 1)

The BMODE pin also controls byte ordering

When

BMODE e 1 big endian byte ordering is selected and when

BMODE e 0 little endian byte ordering is selected

73 BUS OPERATIONS

There are two types of system bus operations 1) SONIC-T

as a slave and 2) SONIC-T as a bus master When

SONIC-T is a slave (eg a CPU accessing SONIC-T regis-

ters) all transfers are non-DMA When SONIC-T is a bus

master (eg SONIC-T accessing receive or transmit buffer

descriptor areas) all transfers are block transfers using

SONIC-T’s on-chip DMA

This section describes the

SONIC-T bus operations Pay special attention to all sec-

tions labeled as ‘‘Note’’ These conditions must be met for

proper bus operation

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