DP83936AVF datasheet(18/104 Pages) NSC

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30 Functional Description (Continued)

Serializer

After data has been written into the 32-byte

transmit FIFO the serializer reads byte wide data from the

FIFO and sends a NRZ data stream to the Manchester en-

coder The rate at which data is transmitted is determined

by the transmit clock (TXC) The serialized data is transmit-

ted after the SFD

Preamble Generator

The preamble generator prefixes a

62-bit alternating ‘‘10’’ pattern and a 2-bit ‘‘11’’ SFD pat-

tern at the beginning of each packet This allows receiving

nodes to synchronize to the incoming data The preamble is

always transmitted in its entirety even in the event of a colli-

sion This assures that the minimum collision fragment is 96

bits (64 bits of normal preamble and 4 bytes or 32 bits of

JAM pattern)

CRC Generator

The CRC generator calculates the 4-byte

FCS field from the transmitted serial data stream If en-

abled the 4-byte FCS field is appended to the end of the

transmitted packet (see Section 46)

For bridging or switched ethernet applications the CRC

Generator can be inhibited by setting bit 13 in the Transmit

Control Register (Section 644) This feature is used when

an ethernet segment has already received a packet with a

CRC appended and needs to forward it another ethernet

segment

Jam Generator

The Jam generator produces a 4-byte pat-

tern of all 1’s to assure that all nodes on the network sense

the collision When a collision occurs the SONIC-T stops

transmitting data and enables the Jam generator If a colli-

sion occurs during the preamble the SONIC-T finishes

transmitting the preamble before enabling the Jam genera-

tor (see Preamble Generator above)

333 Full Duplex Operation

When configured for Full Duplex operation the TSM and

RSM allow simultaneous transmission and reception of

packets In Full Duplex mode the RSM operates as de-

scribed earlier Transmitted packets won’t be monitored

The TSM will operate as described earlier except that the

activity on the receive inputs will be ignored

34 DATA WIDTH AND BYTE ORDERING

The SONIC-T can be programmed to operate with either

32-bit or 16-bit wide memory The data width is configured

during initialization by programming the DW bit in the Data

Configuration Register (DCR) (see Section 642) If the

16-bit data path is selected data is driven on pins D15 – D0

The SONIC-T also provides both Little Endian and Big Endi-

an byte-ordering capability for compatibility with NationalIn-

tel or Motorola microprocessors respectively by selecting

the proper level on the Bus Mode (BMODE) pin

Little Endian (NationalIntel) Mode (BMODE e 0) The

byte orientation for received and transmitted data in the Re-

ceive Buffer Area (RBA) and Transmit Buffer Area (TBA) of

system memory is as follows

16-Bit Word

Byte 1

Byte 0

MSB

LSB

32-Bit Long Word

Byte 3

Byte 2

Byte 1

Byte 0

MSB

LSB

Big Endian (Motorola) Mode (BMODE e 1)

The byte ori-

entation for received and transmitted data in the RBA and

TBA is as follows

16-Bit Word

Byte 0

Byte 1

LSB

MSB

32-Bit Long Word

Byte 0

Byte 1

Byte 2

Byte 3

LSB

MSB

35 FIFO AND CONTROL LOGIC

The SONIC-T incorporates two independent 32-byte FIFOs

for transferring data tofrom the system interface and from

to the network The FIFOs providing temporary storage of

data free the host system from the real-time demands on

the network

The way in which the FIFOS are emptied and filled is con-

trolled by the FIFO threshold values and the Block Mode

Select bits (BMS) (see Section 642) The threshold values

determine how full or empty the FIFOs are allowed to be

before the SONIC-T will request access of the bus to get

more data from memory or buffer more data to memory

When Block Mode is enabled the number of bytes trans-

ferred is determined by the threshold value For example if

the threshold for the receive FIFO is 4 words then the SON-

IC-T will always transfer 4 words from the receive FIFO to

memory If EmptyFill mode is enabled however the num-

ber of bytes transferred is the number required to fill the

transmit FIFO or empty the receive FIFO The manner in

which the threshold affects reception and transmission of

packets is discussed below in Sections 351 and 352

351 Receive FIFO

To accommodate the different transfer rates the receive

FIFO

(Figure 3-8) serves as a buffer between the 8-bit net-

work (deserializer) interface and the 1632-bit system inter-

face The FIFO is arranged as a 4-byte wide by 8 deep

memory array (8-long words or 32 bytes) controlled by

three sections of logic During reception the Byte Ordering

logic directs the byte stream from the deserializer into the

FIFO using one of four write pointers Depending on the

selected byte-ordering mode data is written either least sig-

nificant byte first or most significant byte first to accommo-

date little or big endian byte-ordering formats respectively

As data enters the FIFO the Threshold Logic monitors the

number of bytes written in from the deserializer The pro-

grammable threshold (RFT10 in the Data Configuration

words (or long words) written into the FIFO from the MAC

unit before a direct memory access (DMA) request for sys-

tem memory occurs When the threshold is reached the

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