DP83936AVF datasheet(9/104 Pages) NSC

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20 Pin Description (Continued)

TABLE 2-1 Pin Description

(Continued)

Symbol

Driver

Direction

Description

Type

BUS INTERFACE PINS (BOTH BUS MODES)

(Continued)

SAS

SLAVE ADDRESS STROBE

The system asserts this pin to latch the register address on lines

RA0 – RA5

TRI

O Z

DATA STROBE

When the SONIC-T is bus master it drives this pin low during a read cycle to

indicate that the slave device may drive data onto the bus in a write cycle this pin indicates that

the SONIC-T has placed valid data onto the bus

BRT

BUS RETRY

When the SONIC-T is bus master the system asserts this signal to rectify a

potentially correctable bus error This pin has two modes Mode 1 (the LBR in the Data

Configuration Register is set to 0) Assertion of this pin forces the SONIC-T to terminate the

current bus cycle and will repeat the same cycle after BRT has been deasserted Mode 2 (the

LBR bit in the Data Configuration register is set to 1) Assertion of this signal forces the SONIC-T

to retry the bus operation as in Mode 1 However the SONIC-T will not continue DMA operations

until the BR bit in the ISR is reset

ECS

TRI

O Z

EARLY CYCLE START

This output gives the system earliest indication that a memory operation

is occurring This signal is driven low at the rising edge of T1 and high at the falling edge of T1

SHARED-MEMORY ACCESS PINS

MREQ

MEMORY REQUEST

The system asserts this signal low when it attempts to access the shared-

buffer RAM The on-chip arbiter resolves accesses between the system and the SONIC-T

Note

Both CS and MREQ must not be asserted concurrently If these signals are successively

asserted there must be at least two bus clocks between the deasserting edge of the first signal

and the asserting edge of the second signal

SMACK

SLAVE AND MEMORY ACKNOWLEDGE

SONIC-T asserts this dual function pin low in response

to either a Chip Select (CS) or a Memory Request (MREQ) when the SONIC-T’s registers or its

buffer memory is available for accessing This pin can be used for enabling bus drivers for dual-

bus systems

BUS INTERFACE PINS (NATIONALINTEL MODE BMODE e 0)

ADS

TRI

O Z

ADDRESS STROBE (ADS)

The rising edge indicates valid status and address

MWR

TRI

O Z

MEMORY WRITEREAD STROBE MWR

When the SONIC-T has acquired the bus this signal

indicates the direction of the data transfer The signal is low during a read cycle and high during a

write cycle

INT

INTERRUPT (INT)

Indicates that an interrupt (if enabled) is pending from one of the sources

indicated by the Interrupt Status register Interrupts that are disabled in the Interrupt Mask register

will not activate this signal

HOLD

HOLD REQUEST (HOLD)

The SONIC-T drives this pin high when it intends to use the bus and is

driven low when inactive

HLDA

HOLD ACKNOWLEDGE (HLDA)

This signal is used to inform the SONIC-T that it has attained

the bus When the system asserts this pin high the SONIC-T has gained ownership of the bus

BGACK

TRI

O Z

BUS GRANT ACKNOWLEDGE

This pin is only used when BMODE e 1

SWR

SLAVE READWRITE STROBE (SWR)

The system asserts this pin to indicate whether it will

read from or write to the SONIC-T’s registers This signal is asserted low during a read and high

during a write

RDYi

READY INPUT (RDYi BMODE e 0)

When the SONIC-T is a bus master the system asserts this

signal high to insert wait-states and low to terminate the memory cycle This signal is sampled

synchronously or asynchronously depending on the state of the SBUS bit (See Sections 735

and 642 for details)

RDYo

READY OUTPUT (RDYo)

When a register is accessed the SONIC-T asserts this signal to

terminate the slave cycle

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