TMS320F2810PBKA datasheet(104/173 Pages) TI

104 / 173 page

Result Registers

EVB

S/W

ADC Control Registers

70B7h

70B0h

70AFh

70A8h

Result Reg 15

Result Reg 8

Result Reg 7

Result Reg 1

Result Reg 0

12-Bit

ADC

Module

Analog

MUX

EVA

S/W

ADCINA0

ADCINA7

ADCINB0

ADCINB7

ADCSOC

System

Control Block

High-Speed

Prescaler

HSPCLK

C28x

SYSCLKOUT

S/H

ADCENCLK

Sequencer 2

Sequencer 1

SOC

104

TMS320F2810, TMS320F2811, TMS320F2812

SPRS174U – APRIL 2001 – REVISED JULY 2019

www.ti.com

Submit Documentation Feedback

Product Folder Links: TMS320F2810 TMS320F2811 TMS320F2812

Detailed Description

Figure 6-4. Block Diagram of the F281x ADC Module

To obtain the specified accuracy of the ADC, proper board layout is critical. To the best extent possible,

traces leading to the ADCIN pins should not run in close proximity to the digital signal paths. This is to

minimize switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper

isolation techniques must be used to isolate the ADC module power pins (VDDA1/VDDA2, AVDDREFBG)

from the digital supply. For better accuracy and ESD protection, unused ADC inputs should be connected

to analog ground.

Notes:

1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the ADC module is

controlled by the high-speed peripheral clock (HSPCLK).

2. The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as

follows:

ADCENCLK: On reset, this signal will be low. While reset is active-low (XRS) the clock to the register

will still function. This is necessary to make sure all registers and modes go into their default reset

state. The analog module will, however, be in a low-power inactive state. As soon as reset goes high,

then the clock to the registers will be disabled. When the user sets the ADCENCLK signal high, then

the clocks to the registers will be enabled and the analog module will be enabled. There will be a

certain time delay (ms range) before the ADC is stable and can be used.

HALT: This signal only affects the analog module. It does not affect the registers. If low, the ADC

module is powered. If high, the ADC module goes into low-power mode. The HALT mode will stop the

clock to the CPU, which will stop the HSPCLK. Therefore the ADC register logic will be turned off

indirectly.

TMS320F2810PBKA Datasheet(PDF) 104 Page - Texas Instruments

TMS320F2810PBKA Datasheet(HTML) 104 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL