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26HS01GTAM03 Datasheet(PDF) 124 Page - Infineon Technologies AG |
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26HS01GTAM03 Datasheet(HTML) 124 Page - Infineon Technologies AG |
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124 / 166 page  Datasheet 124 of 166 002-12337 Rev. *Y 2022-01-18 256Mb/512Mb/1Gb SEMPER™ Flash HYPERBUS™ interface, 1.8V/3.0V Transaction table 6Transaction table 6.1 HYPERBUS™ transaction table Table 120 HYPERBUS™ transaction description Transaction name Description Cycles RDMARY_1_0 Read transaction allows reading out the memory array data at the given address and places it on DQ[7:0]. 1 ENSPIM_3_0 Enter SPI transaction changes the device interface from HYPERBUS™ to Legacy (x1) SPI. 3 SRASOE_1_0 Software Reset / ASO Exit transaction returns the device to reading memory array data mode when device is in ASO. It also clears SR0[5,4,3,1,0] when the device is not busy or is in the middle of a transaction sequence or in an ASO. 1 ENTDPD_3_0 Enter Deep Power Down Mode transaction moves the device in the lowest power consumption mode. 3 RDVSTR_2_0 Read Status Register transaction allows the Status Register contents to be read with data placed on DQ[7:0]. 2 CLVSTR_1_0 Clear Status Register Failure Flags transaction resets all failure flags being reported. 1 PRNPOR_4_0 Program Nonvolatile POR Timer Register transaction programs into the 16-bit POR Time Register the value which is multiplied by tPOR_CK (25 to 42 µs) to define the length of extension to the RSTO# pulse beyond tVCS with data placed on DQ[7:0]. 4 RDNPOR_4_0 Read Nonvolatile POR Timer Register transaction allows reading the contents of the 16-bit POR Time Register and places it on DQ[7:0]. 4 PGVINC_4_0 Program Volatile Interrupt Configuration Register transaction programs the 16-bit Interrupt Configu- ration Register with data placed on DQ[7:0]. 4 RDVINC_4_0 Read Volatile Interrupt Configuration Register transaction allows reading the contents of the 16-bit Interrupt Configuration Register and places it on DQ[7:0]. 4 PGVINS_4_0 Program Volatile Interrupt Status Register transaction programs the 16-bit Interrupt Status Register with data placed on DQ[7:0]. 4 RDVINS_4_0 Read Volatile Interrupt Status Register transaction allows reading the contents of the 16-bit Interrupt Status Register and places it on DQ[7:0]. 4 PGVCR1_4_0 Program Volatile Configuration Register 1 transaction programs the 16-bit Volatile Configuration Register 0 with data placed on DQ[7:0]. 4 PGVCR2_4_0 Program Volatile Configuration Register 2 transaction programs the 16-bit Volatile Configuration Register 1 with data placed on DQ[7:0]. 4 RDVCR1_4_0 Read Volatile Configuration Register 1 transaction allows reading the contents of the 16-bit Volatile Configuration Register 0 and places it on DQ[7:0]. 4 RDVCR2_4_0 Read Volatile Configuration Register 2 transaction allows reading the contents of the 16-bit Volatile Configuration Register 1 and places it on DQ[7:0]. 4 PGNCR1_4_0 Program Nonvolatile Configuration Register 1 transaction programs the 16-bit Nonvolatile Configuration Register 0 with data placed on DQ[7:0]. 4 PGNCR2_4_0 Program Nonvolatile Configuration Register 2 transaction programs the 16-bit Nonvolatile Configuration Register 1 with data placed on DQ[7:0]. 4 ERNC12_3_0 Erase Nonvolatile Configuration Registers 1 and 2 transaction erases the contents of the two 16-bit Nonvolatile Configuration registers (0, 1). 3 RDNCR1_4_0 Read Nonvolatile Configuration Register 1 transaction allows reading the contents of the 16-bit Nonvol- atile Configuration Register 0 and places it on DQ[7:0]. 4 RDNCR2_4_0 Read Nonvolatile Configuration Register 2 transaction allows reading the contents of the 16-bit Nonvol- atile Configuration Register 1 and places it on DQ[7:0]. 4 PGWORD_4_0 Program Word transaction programs the data word (0's) supplied on DQ[7:0] in the addressed memory array. 4 LDBUFR_6_0 Load Write Buffer transaction loads up to 256/512 bytes of data (0's) supplied on DQ[7:0] in the write buffer. 6 PGBFCM_1_0 Program Write Buffer Confirm transaction tells the device to program the data loaded into the write buffer into the addressed memory array. 1 RSTWBA_3_0 Reset Write to Buffer Abort transaction resets the Write Buffer Abort Status Flag (WRBFAB - STRV[3]) and Programming Error Status Flag (PRGERR - STRV[4]) in the Status Register. 3 ERCHIP_6_0 Erase Chip transaction sets all bits to 1 (all bytes are FFh) inside the entire flash memory array. 6 ERSCTR_6_0 Erase Sector transaction sets all the bits of an addressed 256KB sector or a 4KB sector to 1 (all bytes are FFh). 6 BLKCHK_1_0 Blank Check transaction confirms if the selected Flash Memory Array sector is fully erased. ERSERR (STRV[5]- Bit 5 of the Status Register) will be cleared to 0 if the sector is erased and set to 1 if not erased. 1 EVERST_1_0 Evaluate Erase Status transaction verifies that the last erase operation on the addressed sector was completed successfully. f the selected sector was successfully erased the SESTAT (STRV[5]- Bit 0 of the Status Register) is set to 1. 1 SPERSE_1_0 Suspend Erase transaction allows the system to interrupt an erase operation. 1 |
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