26HS01GTAM03 datasheet(154/166 Pages) INFINEON

154 / 166 page

Datasheet

154 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Device identification

134h

(SA) + 9Ah

JEDEC basic flash

parameter

DWORD-14

F7h

Bits 7:4 = RFU = Fh

Bit 3:2 = Status Register Polling Device Busy = 01b: Legacy status polling supported =

Use legacy polling by reading the Status Register with 05h instruction and checking

WIP bit[0] (0 = ready; 1 = busy).

Bits 1:0 = RFU = 11b

135h

66h

Bit 31 = DPD Supported = Supported = 0

Bits 30:23 = Enter DPD Instruction = B9h

Bits 22:15 = Exit DPD Instruction not supported = 00h

Bits 14:13 = Exit DPD to next operation delay units = (00b: 128ns, 01b: 1μs, 10b: 8μs,

11b: 64μs)

= 64μs = 11b

Bits 12:8 = Exit DPD to next operation delay count = 00110, Exit DPD to next operation

delay

= (count+1) * units = (6 + 1) * 64 μs = 448 μs

136h

(SA) + 9Bh

80h

137h

5Ch

138h

(SA) + 9Ch

JEDEC basic flash

parameter

DWORD-15

00h

Bits 31:24 = Reserved = FFh

Bit 23 = Hold or RESET Disable = not supported = 0b

Bits 22:0 = Not supported = 000000h

139h

00h

13Ah

(SA) + 9Dh

00h

13Bh

FFh

13Ch

(SA) + 9Eh

JEDEC basic flash

parameter

DWORD-16

F9h

Bit 7 = Reserved = 1

Bits 6:0 = Volatile or Nonvolatile Register and Write Enable Instruction for Status

= xxx_xxx1b: Nonvolatile Status Register 1, powers-up to last written value, use

instruction 06h to enable write.

+ xxx_1xxxb: Nonvolatile/Volatile Status Register 1 powers-up to last written value in

the nonvolatile status register, use instruction 06h to enable write to nonvolatile

status register. Volatile status register may be activated after power-up to override

the nonvolatile status register, use instruction 50h to enable write and activate the

volatile status register.

+ xx1_xxxxb: Status Register 1 contains a mix of volatile and nonvolatile bits. The 06h

instruction is used to enable writing of the register.

+ x1x_xxxxb: Reserved

+ 1xx_xxxxb: Reserved

= 1111001b

13Dh

10h

13Eh

(SA) + 9Fh

F8h

Bits 31:24 = Enter 4-byte Addressing

+ xx1x_xxxxb: Supports dedicated 4-Byte address instruction set. Refer to the vendor

datasheet for the instruction set definition.

+ 1xxx_xxxxb: Reserved

= 1010_0000b

Bits 23:14 = Exit 4-Byte Addressing

= xx_xx1x_xxxxb: Hardware reset

+ xx_x1xx_xxxxb: Software reset (see bits 13:8 in this DWORD)

+ xx_1xxx_xxxxb: Power cycle

+ x1_xxxx_xxxxb: Reserved

+ 1x_xxxx_xxxxb: Reserved

= 11_1110_0000b

Bits 13:8 = Soft Reset and Rescue Sequence Support

+ x1_xxxxb: issue reset enable instruction 66h, then issue reset instruction 99h. The

reset enable, reset sequence may be issued on 1, 2, or 4 wires depending on the device

operating mode.

= 010000b

13Fh

A0h

140h

(SA) + A0h

JEDEC basic flash

parameter

DWORD-17

00h

Not Supported

141h

00h

142h

(SA) + A1h

00h

143h

00h

144h

(SA) + A2h

JEDEC basic flash

parameter

DWORD-18

00h

Bit 31 = 0b

Bit 30:29 = 10b

Bit 28 = 0b

Bit 27:26 = Not supported = 00b

Bits 25:24 = 00b

Bit 23 = JEDEC SPI Protocol Reset Supported = 1b

Bits 22:18 = 01111b

Bits 17:0 = Reserved = 00000h

145h

00h

146h

(SA) + A3h

BCh

147h

40h

148h

(SA) + A4h

JEDEC basic flash

parameter

DWORD-19

00h

Not Supported

149h

14Ah

(SA) + A5h

14Bh

Table 131

JEDEC SFDP Rev D parameter table (Continued)

Byte

address

(x1 SPI)

Word address

(x8 HB)

SFDP DWORD

name

Data

Description

26HS01GTAM03 Datasheet(PDF) 154 Page - Infineon Technologies AG

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