MC9S08DN60F1CLF datasheet(28/356 Pages) FREESCALE

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Chapter 2 Pins and Connections

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

Whenever any reset is initiated (whether from an external signal or from an internal system), the RESET

pin is driven low for about 34 bus cycles. The reset circuitry decodes the cause of reset and records it by

setting a corresponding bit in the system reset status register (SRS).

2.2.4

Background / Mode Select (BKGD/MS)

While in reset, the BKGD/MS pin functions as a mode select pin. Immediately after reset rises, the pin

functions as the background pin and can be used for background debug communication. While functioning

as a background or mode select pin, the pin includes an internal pull-up device, input hysteresis, a standard

output driver, and no output slew rate control.

If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset.

If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD low

during the rising edge of reset which forces the MCU to active background mode.

The BKGD/MS pin is used primarily for background debug controller (BDC) communications using a

custom protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s

BDC clock could be as fast as the bus clock rate, so there should never be any signiﬁcant capacitance

connected to the BKGD/MS pin that could interfere with background serial communications.

Although the BKGD/MS pin is a pseudo open-drain pin, the background debug communication protocol

provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from

cables and the absolute value of the internal pull-up device play almost no role in determining rise and fall

times on the BKGD/MS pin.

2.2.5

ADC Reference Pins (VREFH, VREFL)

The VREFH and VREFL pins are the voltage reference high and voltage reference low inputs, respectively,

for the ADC module.

2.2.6

General-Purpose I/O and Peripheral Ports

The MC9S08DN60 Series series of MCUs support up to 53 general-purpose I/O pins and 1 input-only pin,

which are shared with on-chip peripheral functions (timers, serial I/O, ADC, etc.).

When a port pin is conﬁgured as a general-purpose output or a peripheral uses the port pin as an output,

software can select one of two drive strengths and enable or disable slew rate control. When a port pin is

conﬁgured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a

pull-up device. Immediately after reset, all of these pins are conﬁgured as high-impedance general-purpose

inputs with internal pull-up devices disabled.

When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is

read from port data registers even though the peripheral module controls the pin direction by controlling

the enable for the pin’s output buffer. For information about controlling these pins as general-purpose I/O

pins, see Chapter 6, “Parallel Input/Output Control.”

MC9S08DN60F1CLF Datasheet(PDF) 28 Page - Freescale Semiconductor, Inc