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MC9S08DN60F1CLF Datasheet(PDF) 91 Page - Freescale Semiconductor, Inc |
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MC9S08DN60F1CLF Datasheet(HTML) 91 Page - Freescale Semiconductor, Inc |
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91 / 356 page ![]() Chapter 6 Parallel Input/Output Control MC9S08DN60 Series Data Sheet, Rev 3 Freescale Semiconductor 91 6.5.2.7 Port B Interrupt Pin Select Register (PTBPS) 6.5.2.8 Port B Interrupt Edge Select Register (PTBES) 76543210 R PTBPS7 PTBPS6 PTBPS5 PTBPS4 PTBPS3 PTBPS2 PTBPS1 PTBPS0 W Reset: 00000000 Figure 6-17. Port B Interrupt Pin Select Register (PTBPS) Table 6-15. PTBPS Register Field Descriptions Field Description 7:0 PTBPS[7:0] Port B Interrupt Pin Selects — Each of the PTBPSn bits enable the corresponding port B interrupt pin. 0 Pin not enabled as interrupt. 1 Pin enabled as interrupt. 76543210 R PTBES7 PTBES6 PTBES5 PTBES4 PTBES3 PTBES2 PTBES1 PTBES0 W Reset: 00000000 Figure 6-18. Port B Edge Select Register (PTBES) Table 6-16. PTBES Register Field Descriptions Field Description 7:0 PTBES[7:0] Port B Edge Selects — Each of the PTBESn bits serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. 0 A pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation. 1 A pull-down device is connected to the associated pin and detects rising edge/high level for interrupt generation. |
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