MC9S08DN60F1CLF datasheet(92/356 Pages) FREESCALE

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Chapter 6 Parallel Input/Output Control

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

6.5.3

Port C Registers

Port C is controlled by the registers listed below.

6.5.3.1

Port C Data Register (PTCD)

6.5.3.2

Port C Data Direction Register (PTCDD)

76543210

PTCD7

PTCD6

PTCD5

PTCD4

PTCD3

PTCD2

PTCD1

PTCD0

Reset:

00000000

Figure 6-19. Port C Data Register (PTCD)

Table 6-17. PTCD Register Field Descriptions

Field

Description

7:0

PTCD[7:0]

Port C Data Register Bits — For port C pins that are inputs, reads return the logic level on the pin. For port C

pins that are conﬁgured as outputs, reads return the last value written to this register.

Writes are latched into all bits of this register. For port C pins that are conﬁgured as outputs, the logic level is

driven out the corresponding MCU pin.

Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also

conﬁgures all port pins as high-impedance inputs with pull-ups disabled.

76543210

PTCDD7

PTCDD6

PTCDD5

PTCDD4

PTCDD3

PTCDD2

PTCDD1

PTCDD0

Reset:

00000000

Figure 6-20. Port C Data Direction Register (PTCDD)

Table 6-18. PTCDD Register Field Descriptions

Field

Description

7:0

PTCDD[7:0]

Data Direction for Port C Bits — These read/write bits control the direction of port C pins and what is read for

PTCD reads.

0 Input (output driver disabled) and reads return the pin value.

1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn.

MC9S08DN60F1CLF Datasheet(PDF) 92 Page - Freescale Semiconductor, Inc

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