MC9S08DN60F1CLF datasheet(71/356 Pages) FREESCALE

71 / 356 page

Chapter 5 Resets, Interrupts, and General System Control

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

5.8.1

Interrupt Pin Request Status and Control Register (IRQSC)

This direct page register includes status and control bits which are used to conﬁgure the IRQ function,

report status, and acknowledge IRQ events.

76543210

IRQPDD

IRQEDG

IRQPE

IRQF

IRQIE

IRQMOD

IRQACK

Reset

00000000

= Unimplemented or Reserved

Figure 5-2. Interrupt Request Status and Control Register (IRQSC)

Table 5-2. IRQSC Register Field Descriptions

Field

Description

IRQPDD

Interrupt Request (IRQ) Pull Device Disable— This read/write control bit is used to disable the internal

pull-up/pull-down device when the IRQ pin is enabled (IRQPE = 1) allowing for an external device to be used.

0 IRQ pull device enabled if IRQPE = 1.

1 IRQ pull device disabled if IRQPE = 1.

IRQEDG

Interrupt Request (IRQ) Edge Select — This read/write control bit is used to select the polarity of edges or

levels on the IRQ pin that cause IRQF to be set. The IRQMOD control bit determines whether the IRQ pin is

sensitive to both edges and levels or only edges. When the IRQ pin is enabled as the IRQ input and is conﬁgured

to detect rising edges, it has a pull-down. When the IRQ pin is enabled as the IRQ input and is conﬁgured to

detect falling edges, it has a pull-up.

0 IRQ is falling edge or falling edge/low-level sensitive.

1 IRQ is rising edge or rising edge/high-level sensitive.

IRQPE

IRQ Pin Enable — This read/write control bit enables the IRQ pin function. When this bit is set the IRQ pin can

be used as an interrupt request.

0 IRQ pin function is disabled.

1 IRQ pin function is enabled.

IRQF

IRQ Flag — This read-only status bit indicates when an interrupt request event has occurred.

0 No IRQ request.

1 IRQ event detected.

IRQACK

IRQ Acknowledge — This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF).

Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1),

IRQF cannot be cleared while the IRQ pin remains at its asserted level.

IRQIE

IRQ Interrupt Enable — This read/write control bit determines whether IRQ events generate an interrupt

request.

0 Interrupt request when IRQF set is disabled (use polling).

1 Interrupt requested whenever IRQF = 1.

IRQMOD

IRQ Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level

detection. The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt

request events. See Section 5.5.2.2, “Edge and Level Sensitivity” for more details.

0 IRQ event on falling edges or rising edges only.

1 IRQ event on falling edges and low levels or on rising edges and high levels.

MC9S08DN60F1CLF Datasheet(PDF) 71 Page - Freescale Semiconductor, Inc

MC9S08DN60F1CLF Datasheet(HTML) 71 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL