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MC9S08DN60F1CLF Datasheet(PDF) 93 Page - Freescale Semiconductor, Inc |
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MC9S08DN60F1CLF Datasheet(HTML) 93 Page - Freescale Semiconductor, Inc |
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93 / 356 page ![]() Chapter 6 Parallel Input/Output Control MC9S08DN60 Series Data Sheet, Rev 3 Freescale Semiconductor 93 6.5.3.3 Port C Pull Enable Register (PTCPE) NOTE Pull-down devices only apply when using pin interrupt functions, when corresponding edge select and pin select functions are configured. 6.5.3.4 Port C Slew Rate Enable Register (PTCSE) Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew rate control to the desired value to ensure correct operation. 76543210 R PTCPE7 PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0 W Reset: 00000000 Figure 6-21. Internal Pull Enable for Port C Register (PTCPE) Table 6-19. PTCPE Register Field Descriptions Field Description 7:0 PTCPE[7:0] Internal Pull Enable for Port C Bits — Each of these control bits determines if the internal pull-up device is enabled for the associated PTC pin. For port C pins that are configured as outputs, these bits have no effect and the internal pull devices are disabled. 0 Internal pull-up device disabled for port C bit n. 1 Internal pull-up device enabled for port C bit n. 76543210 R PTCSE7 PTCSE6 PTCSE5 PTCSE4 PTCSE3 PTCSE2 PTCSE1 PTCSE0 W Reset: 00000000 Figure 6-22. Slew Rate Enable for Port C Register (PTCSE) Table 6-20. PTCSE Register Field Descriptions Field Description 7:0 PTCSE[7:0] Output Slew Rate Enable for Port C Bits — Each of these control bits determines if the output slew rate control is enabled for the associated PTC pin. For port C pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port C bit n. 1 Output slew rate control enabled for port C bit n. |
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