MC9S08DN60F1CLF datasheet(63/356 Pages) FREESCALE

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MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

Chapter 5

Resets, Interrupts, and General System Control

5.1

Introduction

This section discusses basic reset and interrupt mechanisms and their various sources in the MC9S08DN60

Series. Some interrupt sources from peripheral modules are discussed in greater detail within other

sections of this data sheet. This section gathers basic information about all reset and interrupt sources in

one place for easy reference. A few reset and interrupt sources, including the computer operating properly

(COP) watchdog, are not part of on-chip peripheral systems with their own chapters.

5.2

Features

Reset and interrupt features include:

•

Multiple sources of reset for ﬂexible system conﬁguration and reliable operation

•

Reset status register (SRS) to indicate source of most recent reset

•

Separate interrupt vector for each module (reduces polling overhead); see Table 5-1

5.3

MCU Reset

Resetting the MCU provides a way to start processing from a known set of initial conditions. During reset,

most control and status registers are forced to initial values and the program counter is loaded from the

reset vector (0xFFFE:0xFFFF). On-chip peripheral modules are disabled and I/O pins are initially

conﬁgured as general-purpose high-impedance inputs with pull-up devices disabled. The I bit in the

condition code register (CCR) is set to block maskable interrupts so the user program has a chance to

initialize the stack pointer (SP) and system control settings. (See the CPU chapter for information on the

Interrupt (I) bit.) SP is forced to 0x00FF at reset.

The MC9S08DN60 Series has eight sources for reset:

•

Power-on reset (POR)

•

External pin reset (PIN)

•

Computer operating properly (COP) timer

•

Illegal opcode detect (ILOP)

•

Illegal address detect (ILAD)

•

Low-voltage detect (LVD)

•

Loss of clock (LOC)

•

Background debug forced reset (BDFR)

Each of these sources, with the exception of the background debug forced reset, has an associated bit in

the system reset status register (SRS).

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