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MC9S08DN60F1CLF Datasheet(PDF) 35 Page - Freescale Semiconductor, Inc |
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MC9S08DN60F1CLF Datasheet(HTML) 35 Page - Freescale Semiconductor, Inc |
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35 / 356 page  Chapter 3 Modes of Operation MC9S08DN60 Series Data Sheet, Rev 3 Freescale Semiconductor 35 To maintain I/O states for pins that were configured as general-purpose I/O before entering stop2, the user must restore the contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the pins will switch to their reset states when PPDACK is written. For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O latches are opened. 3.6.3 On-Chip Peripheral Modules in Stop Modes When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate, clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.2, “Stop2 Mode” and Section 3.6.1, “Stop3 Mode” for specific information on system behavior in stop modes. Table 3-2. Stop Mode Behavior Peripheral Mode Stop2 Stop3 CPU Off Standby RAM Standby Standby Flash/EEPROM Off Standby Parallel Port Registers Off Standby ACMP Off Off ADC Off Optionally On1 1 Requires the asynchronous ADC clock and LVD to be enabled, else in standby. IIC Off Standby MCG Off Optionally On2 2 IRCLKEN and IREFSTEN set in MCGC1, else in standby. RTC Optionally On3 3 Requires the RTC to be enabled, else in standby. Optionally On3 SCI Off Standby SPI Off Standby TPM Off Standby Voltage Regulator Off Optionally On4 4 Requires the LVD or BDC to be enabled. XOSC Off Optionally On5 I/O Pins States Held States Held BDM Off6 Optionally On LVD/LVW Off7 Optionally On |
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