MC9S08DN60F1CLF datasheet(48/356 Pages) FREESCALE

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Chapter 4 Memory

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

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Burst programming capability

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Sector erase abort

4.5.2

Program and Erase Times

Before any program or erase command can be accepted, the Flash and EEPROM clock divider register

(FCDIV) must be written to set the internal clock for the Flash and EEPROM module to a frequency

(fFCLK) between 150 kHz and 200 kHz (see Section 4.5.11.1, “Flash and EEPROM Clock Divider

reset initialization. The user must ensure that FACCERR is not set before writing to the FCDIV register.

One period of the resulting clock (1/fFCLK) is used by the command processor to time program and erase

pulses. An integer number of these timing pulses is used by the command processor to complete a program

or erase command.

Table 4-5 shows program and erase times. The bus clock frequency and FCDIV determine the frequency

of FCLK (fFCLK). The time for one cycle of FCLK is tFCLK = 1/fFCLK. The times are shown as a number

of cycles of FCLK and as an absolute time for the case where tFCLK =5 μs. Program and erase times

shown include overhead for the command state machine and enabling and disabling of program and erase

voltages.

4.5.3

Program and Erase Command Execution

The FCDIV register must be initialized after any reset and any error ﬂag is cleared before beginning

command execution. The command execution steps are:

1. Write a data value to an address in the Flash or EEPROM array. The address and data information

from this write is latched into the Flash and EEPROM interface. This write is a required ﬁrst step

in any command sequence. For erase and blank check commands, the value of the data is not

important. For sector erase commands, the address can be any address in the sector of Flash or

EEPROM to be erased. For mass erase and blank check commands, the address can be any address

in the Flash or EEPROM memory. Flash and EEPROM erase independently of each other.

Table 4-5. Program and Erase Times

Parameter

Cycles of FCLK

Time if FCLK = 200 kHz

Byte program

μs

Burst program

μs1

1 Excluding start/end overhead

Sector erase

4000

20 ms

Mass erase

20,000

100 ms

Sector erase abort

μs1

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