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MC9S08DN60F1CLF Datasheet(PDF) 87 Page - Freescale Semiconductor, Inc |
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MC9S08DN60F1CLF Datasheet(HTML) 87 Page - Freescale Semiconductor, Inc |
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87 / 356 page ![]() Chapter 6 Parallel Input/Output Control MC9S08DN60 Series Data Sheet, Rev 3 Freescale Semiconductor 87 6.5.1.7 Port A Interrupt Pin Select Register (PTAPS) 6.5.1.8 Port A Interrupt Edge Select Register (PTAES) 76543210 R PTAPS7 PTAPS6 PTAPS5 PTAPS4 PTAPS3 PTAPS2 PTAPS1 PTAPS0 W Reset: 00000000 Figure 6-9. Port A Interrupt Pin Select Register (PTAPS) Table 6-7. PTAPS Register Field Descriptions Field Description 7:0 PTAPS[7:0] Port A Interrupt Pin Selects — Each of the PTAPSn bits enable the corresponding port A interrupt pin. 0 Pin not enabled as interrupt. 1 Pin enabled as interrupt. 76543210 R PTAES7 PTAES6 PTAES5 PTAES4 PTAES3 PTAES2 PTAES1 PTAES0 W Reset: 00000000 Figure 6-10. Port A Edge Select Register (PTAES) Table 6-8. PTAES Register Field Descriptions Field Description 7:0 PTAES[7:0] Port A Edge Selects — Each of the PTAESn bits serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. 0 A pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation. 1 A pull-down device is connected to the associated pin and detects rising edge/high level for interrupt generation. |
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