MC9S08DN60F1CLF datasheet(16/356 Pages) FREESCALE

16 / 356 page

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

Section Number

Title

Page

15.1.3 Block Diagram ................................................................................................................262

15.2 Signal Description ..........................................................................................................................264

15.2.1 Detailed Signal Descriptions ...........................................................................................264

15.3 Register Deﬁnition .........................................................................................................................268

15.3.1 TPM Status and Control Register (TPMxSC) ................................................................268

15.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) ....................................................269

15.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) ....................................270

15.3.4 TPM Channel n Status and Control Register (TPMxCnSC) ..........................................271

15.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................272

15.4 Functional Description ...................................................................................................................274

15.4.1 Counter ............................................................................................................................274

15.4.2 Channel Mode Selection .................................................................................................276

15.5 Reset Overview ..............................................................................................................................279

15.5.1 General ............................................................................................................................279

15.5.2 Description of Reset Operation .......................................................................................279

15.6 Interrupts ........................................................................................................................................279

15.6.1 General ............................................................................................................................279

15.6.2 Description of Interrupt Operation ..................................................................................280

15.7 The Differences from TPM v2 to TPM v3.....................................................................................281

Chapter 16

Development Support

16.1 Introduction ....................................................................................................................................287

16.1.1 Forcing Active Background ............................................................................................287

16.1.2 Features ...........................................................................................................................288

16.2 Background Debug Controller (BDC) ...........................................................................................288

16.2.1 BKGD Pin Description ...................................................................................................289

16.2.2 Communication Details ..................................................................................................290

16.2.3 BDC Commands .............................................................................................................294

16.2.4 BDC Hardware Breakpoint .............................................................................................296

16.3 On-Chip Debug System (DBG) .....................................................................................................297

16.3.1 Comparators A and B ......................................................................................................297

16.3.2 Bus Capture Information and FIFO Operation ...............................................................297

16.3.3 Change-of-Flow Information ..........................................................................................298

16.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................298

16.3.5 Trigger Modes .................................................................................................................299

16.3.6 Hardware Breakpoints ....................................................................................................301

16.4 Register Deﬁnition .........................................................................................................................301

16.4.1 BDC Registers and Control Bits .....................................................................................301

16.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................303

16.4.3 DBG Registers and Control Bits .....................................................................................304

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