MC9S08DN60F1CLF datasheet(82/356 Pages) FREESCALE

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Chapter 6 Parallel Input/Output Control

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

6.3.2

Edge and Level Sensitivity

A valid edge or level on an enabled port pin will set PTxIF in PTxSC. If PTxIE in PTxSC is set, an interrupt

request will be presented to the CPU. Clearing of PTxIF is accomplished by writing a 1 to PTxACK in

PTxSC provided all enabled port inputs are at their deasserted levels. PTxIF will remain set if any enabled

port pin is asserted while attempting to clear by writing a 1 to PTxACK.

6.3.3

Pull-up/Pull-down Resistors

The port interrupt pins can be conﬁgured to use an internal pull-up/pull-down resistor using the associated

I/O port pull-up enable register. If an internal resistor is enabled, the PTxES register is used to select

whether the resistor is a pull-up (PTxESn = 0) or a pull-down (PTxESn = 1).

6.3.4

Pin Interrupt Initialization

When an interrupt pin is ﬁrst enabled, it is possible to get a false interrupt ﬂag. To prevent a false interrupt

request during pin interrupt initialization, the user should do the following:

1. Mask interrupts by clearing PTxIE in PTxSC.

2. Select the pin polarity by setting the appropriate PTxESn bits in PTxES.

3. If using internal pull-up/pull-down device, conﬁgure the associated pull enable bits in PTxPE.

4. Enable the interrupt pins by setting the appropriate PTxPSn bits in PTxPS.

5. Write to PTxACK in PTxSC to clear any false interrupts.

6. Set PTxIE in PTxSC to enable interrupts.

6.4

Pin Behavior in Stop Modes

Pin behavior following execution of a STOP instruction depends on the stop mode that is entered. An

explanation of pin behavior for the various stop modes follows:

•

Stop2 mode is a partial power-down mode, whereby I/O latches are maintained in their state as

before the STOP instruction was executed. CPU register status and the state of I/O registers should

be saved in RAM before the STOP instruction is executed to place the MCU in stop2 mode. Upon

recovery from stop2 mode, before accessing any I/O, the user should examine the state of the PPDF

bit in the SPMSC2 register. If the PPDF bit is 0, I/O must be initialized as if a power on reset had

occurred. If the PPDF bit is 1, peripherals may require initialization to be restored to their pre-stop

condition. This can be done using data previously stored in RAM if it was saved before the STOP

instruction was executed. The user must then write a 1 to the PPDACK bit in the SPMSC2 register.

Access to I/O is now permitted again in the user application program.

•

In stop3 mode, all I/O is maintained because internal logic circuity stays powered up. Upon

recovery, normal I/O function is available to the user.

MC9S08DN60F1CLF Datasheet(PDF) 82 Page - Freescale Semiconductor, Inc