MC9S08DN60F1CLF datasheet(14/356 Pages) FREESCALE

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MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

Section Number

Title

Page

11.3 Register Deﬁnition .........................................................................................................................196

11.3.1 IIC Address Register (IICA) ...........................................................................................197

11.3.2 IIC Frequency Divider Register (IICF) ...........................................................................197

11.3.3 IIC Control Register (IICC1) ..........................................................................................200

11.3.4 IIC Status Register (IICS) ...............................................................................................201

11.3.5 IIC Data I/O Register (IICD) ..........................................................................................202

11.3.6 IIC Control Register 2 (IICC2) .......................................................................................202

11.4 Functional Description ...................................................................................................................203

11.4.1 IIC Protocol .....................................................................................................................203

11.4.2 10-bit Address .................................................................................................................207

11.4.3 General Call Address ......................................................................................................208

11.5 Resets .............................................................................................................................................208

11.6 Interrupts ........................................................................................................................................208

11.6.1 Byte Transfer Interrupt ....................................................................................................208

11.6.2 Address Detect Interrupt .................................................................................................208

11.6.3 Arbitration Lost Interrupt ................................................................................................208

11.7 Initialization/Application Information ...........................................................................................210

Chapter 12

Serial Peripheral Interface (S08SPIV3)

12.1 Introduction ....................................................................................................................................213

12.1.1 Features ...........................................................................................................................215

12.1.2 Block Diagrams ..............................................................................................................215

12.1.3 SPI Baud Rate Generation ..............................................................................................217

12.2 External Signal Description ...........................................................................................................218

12.2.1 SPSCK — SPI Serial Clock ............................................................................................218

12.2.2 MOSI — Master Data Out, Slave Data In ......................................................................218

12.2.3 MISO — Master Data In, Slave Data Out ......................................................................218

12.2.4 SS — Slave Select ...........................................................................................................218

12.3 Modes of Operation........................................................................................................................219

12.3.1 SPI in Stop Modes ..........................................................................................................219

12.4 Register Deﬁnition .........................................................................................................................219

12.4.1 SPI Control Register 1 (SPIC1) ......................................................................................219

12.4.2 SPI Control Register 2 (SPIC2) ......................................................................................220

12.4.3 SPI Baud Rate Register (SPIBR) ....................................................................................221

12.4.4 SPI Status Register (SPIS) ..............................................................................................222

12.4.5 SPI Data Register (SPID) ................................................................................................223

12.5 Functional Description ...................................................................................................................224

12.5.1 SPI Clock Formats ..........................................................................................................224

12.5.2 SPI Interrupts ..................................................................................................................227

12.5.3 Mode Fault Detection .....................................................................................................227

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