MC9S08DN60F1CLF datasheet(81/356 Pages) FREESCALE

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Chapter 6 Parallel Input/Output Control

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

An output pin can be selected to have high output drive strength by setting the corresponding bit in the

drive strength select register (PTxDSn). When high drive is selected, a pin is capable of sourcing and

sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that

the total current source and sink limits for the MCU are not exceeded. Drive strength selection is intended

to affect the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin

to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load.

Because of this, the EMC emissions may be affected by enabling pins as high drive.

6.3

Pin Interrupts

Port A, port B, and port D pins can be conﬁgured as external interrupt inputs and as an external means of

waking the MCU from stop or wait low-power modes.

The block diagram for each port interrupt logic is shown Figure 6-2.

Figure 6-2. Port Interrupt Block Diagram

Writing to the PTxPSn bits in the port interrupt pin select register (PTxPS) independently enables or

disables each port pin. Each port can be conﬁgured as edge sensitive or edge and level sensitive based on

the PTxMOD bit in the port interrupt status and control register (PTxSC). Edge sensitivity can be software

programmed to be either falling or rising; the level can be either low or high. The polarity of the edge or

edge and level sensitivity is selected using the PTxESn bits in the port interrupt edge select register

(PTxES).

Synchronous logic is used to detect edges. Prior to detecting an edge, enabled port inputs must be at the

deasserted logic level. A falling edge is detected when an enabled port input signal is seen as a logic 1 (the

deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. A rising

edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1 during

the next cycle.

6.3.1

Edge Only Sensitivity

A valid edge on an enabled port pin will set PTxIF in PTxSC. If PTxIE in PTxSC is set, an interrupt request

will be presented to the CPU. Clearing of PTxIF is accomplished by writing a 1 to PTxACK in PTxSC.

PTxESn

CLR

VDD

PTxMOD

PTxIE

PORT

INTERRUPT FF

PTxACK

RESET

SYNCHRONIZER

PTxIF

STOP BYPASS

STOP

BUSCLK

PTxPSn

PTxPS0

PTxES0

PTxn

PTx

INTERRUPT

REQUEST

MC9S08DN60F1CLF Datasheet(PDF) 81 Page - Freescale Semiconductor, Inc

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