MC9S08DN60F1CLF datasheet(79/356 Pages) FREESCALE

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MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

Chapter 6

Parallel Input/Output Control

This section explains software controls related to parallel input/output (I/O) and pin control. The

MC9S08DN60 Series has seven parallel I/O ports which include a total of up to 53 I/O pins and one

input-only pin. See Chapter 2, “Pins and Connections,” for more information about pin assignments and

external hardware considerations of these pins.

Many of these pins are shared with on-chip peripherals such as timer systems, communication systems, or

pin interrupts as shown in Table 2-1. The peripheral modules have priority over the general-purpose I/O

functions so that when a peripheral is enabled, the I/O functions associated with the shared pins are

disabled.

After reset, the shared peripheral functions are disabled and the pins are conﬁgured as inputs

(PTxDDn = 0). The pin control functions for each pin are conﬁgured as follows: slew rate control enabled

(PTxSEn = 1), low drive strength selected (PTxDSn = 0), and internal pull-ups disabled (PTxPEn = 0).

NOTE

•

Not all general-purpose I/O pins are available on all packages. To avoid

extra current drain from ﬂoating input pins, the user’s reset initialization

routine in the application program must either enable on-chip pull-up

devices or change the direction of unconnected pins to outputs so the

pins do not ﬂoat.

•

The PTE1 pin does not contain a clamp diode to VDD and should not be

driven above VDD. The voltage measured on the internally pulled up

PTE1 pin may be as low as VDD – 0.7 V. The internal gates connected

to this pin are pulled all the way to VDD.

6.1

Port Data and Data Direction

Reading and writing of parallel I/Os are performed through the port data registers. The direction, either

input or output, is controlled through the port data direction registers. The parallel I/O port function for an

individual pin is illustrated in the block diagram shown in Figure 6-1.

The data direction control bit (PTxDDn) determines whether the output buffer for the associated pin is

enabled, and also controls the source for port data register reads. The input buffer for the associated pin is

always enabled unless the pin is enabled as an analog function or is an output-only pin.

When a shared digital function is enabled for a pin, the output buffer is controlled by the shared function.

However, the data direction register bit will continue to control the source for reads of the port data register.

When a shared analog function is enabled for a pin, both the input and output buffers are disabled. A value

of 0 is read for any port data bit where the bit is an input (PTxDDn = 0) and the input buffer is disabled.

MC9S08DN60F1CLF Datasheet(PDF) 79 Page - Freescale Semiconductor, Inc