MC9S08DN60F1CLF datasheet(64/356 Pages) FREESCALE

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Chapter 5 Resets, Interrupts, and General System Control

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

5.4

Computer Operating Properly (COP) Watchdog

The COP watchdog is intended to force a system reset when the application software fails to execute as

expected. To prevent a system reset from the COP timer (when it is enabled), application software must

reset the COP counter periodically. If the application program gets lost and fails to reset the COP counter

before it times out, a system reset is generated to force the system back to a known starting point.

After any reset, the COP watchdog is enabled (see Section 5.8.4, “System Options Register 1 (SOPT1),”

for additional information). If the COP watchdog is not used in an application, it can be disabled by

clearing COPT bits in SOPT1.

The COP counter is reset by writing 0x55 and 0xAA (in this order) to the address of SRS during the

selected timeout period. Writes do not affect the data in the read-only SRS. As soon as the write sequence

is done, the COP timeout period is restarted. If the program fails to do this during the time-out period, the

MCU will reset. Also, if any value other than 0x55 or 0xAA is written to SRS, the MCU is immediately

reset.

The COPCLKS bit in SOPT2 (see Section 5.8.5, “System Options Register 2 (SOPT2),” for additional

information) selects the clock source used for the COP timer. The clock source options are either the bus

clock or an internal 1-kHz clock source. With each clock source, there are three associated time-outs

controlled by the COPT bits in SOPT1. Table 5-6 summaries the control functions of the COPCLKS and

COPT bits. The COP watchdog defaults to operation from the 1-kHz clock source and the longest time-out

(210 cycles).

When the bus clock source is selected, windowed COP operation is available by setting COPW in the

SOPT2 register. In this mode, writes to the SRS register to clear the COP timer must occur in the last 25%

of the selected timeout period. A premature write immediately resets the MCU. When the 1-kHz clock

source is selected, windowed COP operation is not available.

The COP counter is initialized by the ﬁrst writes to the SOPT1 and SOPT2 registers and after any system

reset. Subsequent writes to SOPT1 and SOPT2 have no effect on COP operation. Even if the application

will use the reset default settings of COPT, COPCLKS, and COPW bits, the user should write to the

write-once SOPT1 and SOPT2 registers during reset initialization to lock in the settings. This will prevent

accidental changes if the application program gets lost.

The write to SRS that services (clears) the COP counter should not be placed in an interrupt service routine

(ISR) because the ISR could continue to be executed periodically even if the main application program

fails.

If the bus clock source is selected, the COP counter does not increment while the MCU is in background

debug mode or while the system is in stop mode. The COP counter resumes when the MCU exits

background debug mode or stop mode.

If the 1-kHz clock source is selected, the COP counter is re-initialized to zero upon entry to either

background debug mode or stop mode and begins from zero upon exit from background debug mode or

stop mode.

MC9S08DN60F1CLF Datasheet(PDF) 64 Page - Freescale Semiconductor, Inc