MC9S08DN60F1CLF datasheet(67/356 Pages) FREESCALE

67 / 356 page

Chapter 5 Resets, Interrupts, and General System Control

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

The IRQ pin, when enabled, defaults to use an internal pull device (IRQPDD = 0), the device is a pull-up

or pull-down depending on the polarity chosen. If the user desires to use an external pull-up or pull-down,

the IRQPDD can be written to a 1 to turn off the internal device.

BIH and BIL instructions may be used to detect the level on the IRQ pin when the pin is conﬁgured to act

as the IRQ input.

5.5.2.2

Edge and Level Sensitivity

The IRQMOD control bit reconﬁgures the detection logic so it detects edge events and pin levels. In the

edge and level detection mode, the IRQF status ﬂag becomes set when an edge is detected (when the IRQ

pin changes from the deasserted to the asserted level), but the ﬂag is continuously set (and cannot be

cleared) as long as the IRQ pin remains at the asserted level.

5.5.3

Interrupt Vectors, Sources, and Local Masks

Table 5-1 provides a summary of all interrupt sources. Higher-priority sources are located toward the

bottom of the table. The high-order byte of the address for the interrupt service routine is located at the

ﬁrst address in the vector address column, and the low-order byte of the address for the interrupt service

routine is located at the next higher address.

When an interrupt condition occurs, an associated ﬂag bit becomes set. If the associated local interrupt

enable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in

the CCR) is 0, the CPU will ﬁnish the current instruction; stack the PCL, PCH, X, A, and CCR CPU

registers; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt.

Processing then continues in the interrupt service routine.

MC9S08DN60F1CLF Datasheet(PDF) 67 Page - Freescale Semiconductor, Inc